is to confirm the initial pen-touch. note that, when the input to the c-mos logic is blocked by tsicr0, this bit is always 1. [description] a. < pxen > 0 1 0 off off 1 on off a ddress = (0xf006_0000) + (0x01f0) pxd ( internal p ull-down resistor ) on/off
tmpa901cm tmpa901cm- 678 2010-07-29 2. tsicr1 (tsi control register1) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7] dbc7 r/w 0y0 0y0: disable 0y1: enable [6] db1024 r/w 0y0 1024 [5] db256 r/w 0y0 256 [4] db64 r/w 0y0 64 [3] db8 r/w 0y0 8 [2] db4 r/w 0y0 4 [1] db2 r/w 0y0 2 [0] db1 r/w 0y0 1 de-bounce time is set by the ?(n 64-16)/f pclk ? formula. ?n? is the sum of the numbers obtained when 1 is set in bit 6 to bit 0. (note 2) note 1: since several pulses of f pclk are used to synchronize the pd6/inta si gnal before it is input to the counter circuit for counting the debounce time, the actual debounce time is the abov e period plus an extra synchronization period. note 2: for example, when tsicr1 = 0x95, n = 64 + 4 + 1 =69. in this case, the debouce time is 44 s plus an extra synchronization period when f pclk = 100 mhz. a ddress = (0xf006_0000) + (0x01f4)
tmpa901cm tmpa901cm- 679 2010-07-29 3.20.3 touch detection procedure the touch detection procedure includes the pr ocedures starting from when the pen is touched onto the touch screen and until the pen-touch is detected. touching the screen generates the interrupt in ta and terminates this procedure. after an x/y position measuring at inta interrupt routine, and an x/y position measuring procedure is terminated, return to this procedure to wait for the next touch. when waiting for a touch with no contact, set only the spy switch to on and set all other three switches (smy, spx, smx) to off. at this time, the pull-down resistor built in the pd6/inta/px pin is set to on. in this state, because the internal x- and y-direction resistors in the touch screen are not connected, the pd6/inta/px pin is set to low by the internal pull-down resistor (pxd), generating no inta interrupt. when a next pen-touch is given, the x- and y-direction internal resistors in the touch screen are connected, which sets the pd6/inta/px pin to high and generates an inta interrupt. to avoid generating more than one inta interrupt by one pen-touch, the de-bounce circuit as shown below is provided. setting de-bounce time in the tsicr1 register ignores pulses whose time equals to or is below the set time. the de-bounce circuit detects a rising of signal to count up a set de-bounce counter time and then captures the signal into the inside after counting. when the signal turns to ?l? during counting, the counter is cleared, st arting to wait for a rising edge again. figure 3.20.3 block diagram of touch detection de-bounce circuit input enable pmc block pd6/inta avcc3ad avss3ad 50k tsicr1 tsicr0 tsicr0 tsicr1 gpiod block 1 0 note: supportable inttsi rising edge interrupt only by touch detection. gpiod tsicr0 on (pull down) off (spx) ints [5] interrupt setting interrupt clear gpiodic intta 0 1 gpiodfr2 tsicr0 fixed low inttsi to interrupt controller
tmpa901cm tmpa901cm- 680 2010-07-29 figure 3.20.4 timing diagram of de-bounce circuit inta reset the de-bounce time counter. pd6/intsi pin start the de-bounce time counter. de-bounce time de-bounce time the de-bounce time counter matches with a specified de-bounce time, which generates an inta interrupt. a fter the pen is released, an inta interrupt can be received again. de-bounce time no inta interrupt is generated due to edge interrupt even though the de-bounce time counter matc hes a specified de-bouce time.
tmpa901cm tmpa901cm- 681 2010-07-29 3.20.4 x/y position measuring procedure during the routine of pen-touch and inta interrupt generation, execute a pen position measuring following the procedure below: make the spx and smx switches on, and the spy and smy switches off. with this setting, an analog voltage that shows the x position will be input to the pd5/my/an5 pin. the x-position coordinate can be measur ed by converting this voltage into digital code using the ad converter. make the spy and smy switches on, and the spx and smx switches off. with this setting, an analog voltage that shows the y position will be input to the pd4/mx/an4 pin. the y-position coordinate can be measured by converting this voltage into digital code using the ad converter. the analog voltage which is input to the an5 and an4 pins during the x and y position measurement above can be determined with the ratio between the on resistance value of the switch in the tmpa900cm and the resistance value in the touch screen as shown in figure3.20.5 t herefore, even when to uchin g an end area on the touch screen, the analog input voltage will be neither 3.3 v nor 0 v. note that the rate of each resistance varies . remember to take this into consideration during designing. it is also recommended that an average taken from several ad conversions performed if required be adopted as the final correct value. figure3.20.5 analog input voltage calculation values r2 r1 a n4 (an5) pin touch point touch screen resistor : rty (rtx) the resistance depends on the touch screen. smy (smx) on-resistor: rmy (rmx) 10 (typ.) spy(spx) on-resistor: rpy (rpx) 10 (typ.) a vcc3ad = 3.3 v [analog input voltage to the an4 and an5 pins: formula to calculate e1] e1 = ((r2 + rmy) / (rpy + rty + rmy)) avcc3ad[v] example) where avcc3ad = 3.3 v, rpy = rmy = 10 r1 = 400 and r2 = 100 e1 = ((100 + 10) / (10 + 400 + 100 + 10) 3.3 = 0.698 v note 1: an x-coordinate position can be calculated in the same way though above formula is for y-coordinate position. note 2: rty = r1 + r2
tmpa901cm tmpa901cm- 682 2010-07-29 3.20.5 flow chart of touch screen interface (tsi) (1) touch detection procedure (2) x/y position measuring procedure figure 3.20.6 flow example for tsi the following pages explain each circuit condition (a), (b) and (c) in the flow chart above: main routine execute the main routine tsicr0 0x98 tsicr1 0xxx (voluntary) inta routine ? tsicr0 0xc5 ? an5 ad conversion ? store the ad conversion result. ? tsicr0 0xca ? an4 ad conversion ? store the ad conversion result. execute the processes by using x/y-coordinate position information still touched? tsicr0  0x88 tsicr0 == 1? return to the main routine. no yes (a) (b) (c)
tmpa901cm tmpa901cm- 683 2010-07-29 (a) main routine: condition of waiting for inta interrupt gpiodfr1  0x00000030 ;pd[6] inta,pd[5]an5 , pd[4]an4 gpiodfr2  0x000000c0 ;pd[7]py , pd[6] px gpiodis  0x00000000 ;set inta edge interrupt gpiodibe  0x00000000 ;set inta single edge gpiodie  0x00000040 ;enable inta gpiodiev  0x00000040 ;set inta positive edge tsicr0  0x00000098 ;[7] enable tsi / pxd on ;[4] inta enable ;[3] spy:on x- a vss3ad ( px/pd6/inta ) (py/pd7) vrefh vrefl pxen pyen mxen myen a n5 a n4 (my/pd5/an5) a vcc3ad (mx/pd4/an4) vrefh vrefl a vcc3ad a vss3ad a d converter touch screen control tsi7 sp y spx smx smy pxd dec. inta ptst internal data bus y+ y- touch screen x+ on on typ.50k tmpa901cm
tmpa901cm tmpa901cm- 684 2010-07-29 (b) inta routine: x-position coordinate measurement (ad conversion start) gpiodic  0x00000040 ;int request clear tsicr0  0x00000085 ;disable inta tsicr0  0x000000c5 ;[7] enable tsi ;[6] pd6/pd7 : disable input ;[2] spx:on , [0] smx:on admod1  0x00000085 ;set an5 admod0  0x00000001 ;start ad conversion x- x- a vss3ad ( px/pd6/inta ) (py/pd7) vrefh vrefl pxen pyen mxen myen a n5 a n4 (my/pd5/an5) a vcc3ad (mx/pd4/an4) vrefh vrefl a vcc3ad a vss3ad a d converter touch screen control tsi7 sp y spx smx smy dec. inta ptst internal data bus y+ y- touch screen x+ tmpa901cm on on pxd typ.50k
tmpa901cm tmpa901cm- 685 2010-07-29 (c) int4 routine: y-position coordinate measurement (ad conversion start) tsicr0  0x000000ca ;[7] enable tsi ;[6] pd6/pd7 : disable input ;[3] spy:on , [1] smy:on admod1  0x00000084 ;set an4 admod0  0x00000001 ;start ad conversion x- a vss3ad ( px/pd6/inta ) (py/pd7) vrefh vrefl pxen pyen mxen myen a n5 a n4 (my/pd5/an5) a vcc3ad (mx/pd4/an4) vrefh vrefl a vcc3ad a vss3ad a d converter touch screen control tsi7 sp y spx smx smy dec. inta ptst internal data bus y+ y- touch screen x+ tmpa901cm on on pxd typ.50k
tmpa901cm tmpa901cm- 686 2010-07-29 3.20.6 considerations for using the tsi 1 recovery from pcm state in pcm state, power supply of tsi circuit is turned off. however, it can recover from pcm state because of the touch detection is inputted to pmc from pd6/inta input pin directly. setting example: bpdrint  0x00000000 ; write 0x00000000 to register ; int status initial ? bparint  0x00000000 ; int status initial bpprint  0x00000000 ; int status initial bsmrint  0x00000000 ; int status initial brtrint  0x00000000 ; int status initial bpdedge  0x00000000 ; rising edge bpdoe  0x000000b0 ; pd7(spy):on ,pd6(spx):off ; pd5(smy):off , pd4(smx):off bpddata  0x00000000 ; pd6(pxd):on (pull down) bpdrele  0x00000040 ; pcm release enable by inta ?  ? ; and other setting before enter pcm ; refer to pmc chapter note: if it is waked up from pcm state by inta, the interrupt edge is usable rising /falling both edges. however, if using with tsi, it recommends using rising edge. 2 port setting when an intermediate voltage between 0v and avcc3ad is converted by the ad converter, the intermediate voltage is also applied to normal c-mos input gates due to the circuit structure. take measures against the floating current to pd6 and pd7 by setting tsicr0 = 1. when the input to the c-mos logic is cut off, tsicr0 that indicates whether or not a pen touch is detected is always set to 1. tsicr0 tsicr0 input enable pmc block pd6/inta avcc3ad 0 1 0 1 bpdoe ??(signal from pmc block bpddata ? (signal from pmc block pcm mode setting = 1 avss3ad 50 k gpiod off on
tmpa901cm tmpa901cm- 687 2010-07-29 3.21 real-time clock/melody alarm generator (rtcmld) 3.21.1 functional overview the circuits include real-time clock, melody and alarm generator block. the base clock is 32 khz low frequency. each circuit function is shown below. 1) melody: ? can generate melody waveforms at any frequency from 4 hz to 5461 hz. 2) alarm: ? can generate eight patterns of alarm output. ? can generate five types of fixed-interval interrupts (1 hz, 2 hz, 64 hz, 512 hz and 8192 hz). 3) rtc: ? 32-bit counter that counts up every second ? compare 32-bits counter value, and generate interrupt requests (resume request to the pmc is also corresponded)
tmpa901cm tmpa901cm- 688 2010-07-29 3.21.2 block diagram ? comparator 12-bit counter mldfrq melody generator mldcntcr clear stop & clear clear apb i/f mldout 15-bit counter interrupt detection inten [1] (8192 hz) inten [2] (512 hz) inten [3] (64 hz) inten [4] (2 hz) inten [5] (1 hz) alarm waveform generation 4096hz clock generation almout pwonreq rtcintr alarm block melody block xtin xtin apb bus xtin almpatern ints[1] almintr control 32768 divider 32bit counter rtc block xtin counter value update value 1 hz rtcdata rtccomp rtcprst a
tmpa901cm tmpa901cm- 689 2010-07-29 3.21.3 operational description 3.23.3.1 melody generator (1) operational overview based on the low-speed clock (32.768 khz), clock waveforms at any frequency from 4 hz to 5461 hz can be generated and output from the mldalm pin. by connecting buzzer etc outside, melody sounds can easily be played. the melody frequency is calculated as below. xtin = 32.768 [khz] melody output waveform f mld [hz] = 32768 / (2 n + 4) melody setting value n = (16384/ f mld ) ? 2 note: the value n is set through the mldfrq register: n = 1 to 4095 (0x001 to 0xfff) setting n = 0 is prohibited. *for the above equation, see the waveform diagram below. (for reference: basic tone scale setting table) tone scale frequency [hz] mldfrq register value: n c 264 0x03c d 297 0x035 e 330 0x030 f 352 0x02d g 396 0x027 a 440 0x023 b 495 0x01f c 528 0x01d figure 3.21.1 melody waveform , compare flag melout 2n + 4 clocks 00 ?? 01 n n + 1 ?????????? ?? ???? 00 01 02 03 counte r compare flag counter cleared by the compare flag n + 2 clocks xtin
tmpa901cm tmpa901cm- 690 2010-07-29 (2) flowchart for melody setting note: the mldfrq in the flowchart can not read. theref ore, switch to the next step after the data was written and the 3-clocks of 32khz (approx. 93 s) passed. in the other registers, switch to the next step after the data was written and confirmed the updated data by data polling. start set mldalmsel = 0y01 mldcntcr 1: melody output 0: melody stopped yes yes 0 1 no melody being output set melody frequency (mldfrq) yes 3 or more xtin clocks elapsed after setting mldfrql no set mldcntcr = 1 end yes no stop melody output set melody frequency (mldfrq) 3 or more xtin clocks elapsed after setting mldfrq mldcntcr 1: melody output 0: melody stopped set mldcntcr=0 0 1 (note) change melody frequency yes no no
tmpa901cm tmpa901cm- 691 2010-07-29 3.23.3.2 alarm generator (1) operational overview at the frequency (4096 hz) di vided based on the low - speed clock (32.768 khz), eight types of alarm waveforms ca n be generated and output from the mldalm pin. by connecting buzzer etc outside, alarm sounds can easily be played. the free-running counter in the alarm generato r can be used to gene rate five types of interval interrupts (1 hz, 2 hz, 64 hz, 512 hz and 8192 hz). (alarm pattern setting table) alm register setting alarm waveform 0x00 fixed at 0 0x01 al1 pattern 0x02 al2 pattern 0x04 al3 pattern 0x08 al4 pattern 0x10 al5 pattern 0x20 al6 pattern 0x40 al7 pattern 0x80 al8 pattern others undefined (setting prohibited)
tmpa901cm tmpa901cm- 692 2010-07-29 example: various alarm waveform patterns 500 ? ms 1 al3 pattern (1 output) 250 ms al8 pattern (1 output) frequency (4096 hz) al1 pattern (continuous output) 31.25 ms 1 second 1 2 8 1 al2 pattern (8 outputs/per second) 62.5 ms 1 second 1 2 1 al4 pattern (2 outputs/per second) 1 second 1 2 1 3 al5 pattern (3 outputs/per second) 1 al6 pattern (1 output) 62.5 ms 1 2 al7 pattern (2 outputs) 31.25 ms 62.5 ms 62.5 ms 62.5 ms 62.5 ms 62.5 ms
tmpa901cm tmpa901cm- 693 2010-07-29 (2) flowchart for alarm generator setting note: the almpatern register in the flowchart can not read. therefore, switch to the next step after the data was written and the 3-clocks of 32khz (approx. 93 s) passed. in the other registers, switch to the next step after the data was written and confirmed the updated data by data polling. start set almcntcr = 0y0 almcntcr 0y1: start yes 0y0 0y0 almcntcr 0y0: clear and stop set mldalmsel = 0y10 3 or more xtin clocks elapsed after setting almpatern set almpatern end 0y1 set almcntcr = 0y1 note note 0y1
tmpa901cm tmpa901cm- 694 2010-07-29 3.21.4 real-time clock (1) operational overview the real-time clock (32 bit counter) can count every second based on the frequency (1 hz) divided from the low-speed clock (32.768 khz). the current count value can be read from the rtcdata register. clock function can be easily realized by comparing the count value with the value set in the rtccomp register, an interrupt can be generated (can also be us ed as the resume signal from pcm (power cut mode) state). the counter value can be changed arbitrarily by setting a value in the rtcprst register. to keep counting time, power supply is always turned on. even if there is no external factor to wakeup from pcm mode, rtc can issue a power resume request to the pmc, the operation of the 1a power supp ly circuit can be resumed.
tmpa901cm tmpa901cm- 695 2010-07-29 (2) flowchart for real-time clock setting note: switch to the next step after the data was written and the 3-clocks of 32 khz (approx. 93 s) passed. start set rtccomp yes yes rtcprst updated set rtccomp rtcprst = rtcdata? set rtcprst end no no yes 3 or more xtin clocks elapsed after setting rtccomp? no (note)
tmpa901cm tmpa901cm- 696 2010-07-29 3.21.5 register descriptions the following lists the sfrs: register name address (base+) description rtcdata 0x0000 rtc data register rtccomp 0x0004 rtc compare register rtcprst 0x0008 rtc preset register mldalminv 0x0100 melody alarm invert register mldalmsel 0x0104 melody alarm signal select register almcntcr 0x0108 alarm counter control register almpatern 0x010c alarm pattern register mldcntcr 0x0110 melody counter control register mldfrq 0x0114 melody frequency register rtcalmintctr 0x0200 rtc alm interrupt control register rtcalmmis 0x0204 rtc alm interrupt status register base address = 0xf003_0000
tmpa901cm tmpa901cm- 697 2010-07-29 1. rtcdata (rtc data register) bit bit symbol type reset value description [31:0] rtccount ro undefined 32-bit counter value [description] a. returns the rtc count value (32 bits) on read. 2. rtccomp (rtc compare register) bit bit symbol type reset value description [31:0] rtccp wo undefined value to be compared with the rtc counter [description] a. a match between the counter value (in steps of 1 hz) and the value in generates an interrupt and power supply resume request. a ddress = (0xf003_0000) + (0x0000) a ddress = (0xf003_0000) + (0x0004)
tmpa901cm tmpa901cm- 698 2010-07-29 3. rtcprst (rtc preset register) bit bit symbol type reset value description [31:0] rtcpr wo undefined rtc counter preset value [description] a. specifies the rtc counter preset value. ? 4. mldalminv (melody alarm signal invert register) bit bit symbol type reset value description [31:1] ? ? undefined read as undefined. write as zero. [0] mlalinv wo 0y0 mldalm output signal inversion 0y0: do not invert 0y1: invert [description] a. selects whether or not to inve rt the melody/alarm output. 5. mldalmsel (melody alarm select register) bit bit symbol type reset value description [31:2] ? ? undefined read as undefined. write as zero. [1:0] mlalsel wo 0y00 output signal select 0y00: stop output 0y01: melody 0y10: alarm 0y11: setting prohibited [description] a. selects the melody or alarm output from mldalm pin. a ddress = (0xf003_0000) + (0x0008) a ddress = (0xf003_0000) + (0x0100) a ddress = (0xf003_0000) + (0x0104)
tmpa901cm tmpa901cm- 699 2010-07-29 6. almcntcr (alarm counter control register) bit bit symbol type reset value description [31:1] ? ? undefined read as undefined. write as zero. [0] almcc r/w 0y0 free-running counter control 0y0: clear and stop 0y1: start [description] a. controls the 15-bit counter for alarm generation. 7. almpatern (alarm pattern register) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7:0] almptsel wo 0x00 alarm pattern setting (see the table below.) [description] a. selects the alarm pattern to be output. ?? [alarm pattern setting values] almptsel setting alarm waveform 0x00 fixed at 0 0x01 al1 pattern 0x02 al2 pattern 0x04 al3 pattern 0x08 al4 pattern 0x10 al5 pattern 0x20 al6 pattern 0x40 al7 pattern 0x80 al8 pattern others undefined (setting prohibited) a ddress = (0xf003_0000) + (0x0108) a ddress = (0xf003_0000) + (0x010c)
tmpa901cm tmpa901cm- 700 2010-07-29 8. mldcntcr (melody counter control register) bit bit symbol type reset value description [31:1] ? ? undefined read as undefined. write as zero. [0] mldcc r/w 0y0 free-running counter control 0y0: clear and stop 0y1: start [description] a. controls the 12-bit counter for melody generation. ?? 9. mldfrq (melody frequency register) bit bit symbol type reset value description [31:12] ? ? undefined read as undefined. write as zero. [11:0] mldf wo 0x000 melody output frequency setting value n: 0x001 to 0xfff [description] a. specifies the counter value (n) for melody output frequency setting. formula: f mld [hz] = 32768/ (2n + 4) a ddress = (0xf003_0000) + (0x0110) a ddress = (0xf003_0000) + (0x0114)
tmpa901cm tmpa901cm- 701 2010-07-29 10. rtcalmintctr (rtc alm interrupt control register) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7] almintclr wo 0y0 alarm interrupt flag clear 0y0: invalid 0y1: clear [6] rtcintclr wo 0y0 rtc interrupt flag clear 0y0: invalid 0y1: clear [5] ainten1 r/w 0y0 alarm (1 hz) interrupt enable 0y0: disable 0y1: enable [4] ainten2 r/w 0y0 alarm (2 hz) interrupt enable 0y0: disable 0y1: enable [3] ainten64 r/w 0y0 alarm (64 hz) interrupt enable 0y0: disable 0y1: enable [2] ainten512 r/w 0y0 alarm (512 hz) interrupt enable 0y0: disable 0y1: enable [1] ainten8192 r/w 0y0 alarm (8192 hz) interrupt enable 0y0: disable 0y1: enable [0] rtcinten r/w 0y0 rtc interrupt enable 0y0: disable 0y1: enable [description] a. clears the enabled alarm interrupt flag. b. clears the enabled rtc interrupt flag. c. enables or disables the alarm (1 hz) interrupt. d. enables or disables the alarm (2 hz) interrupt. e. enables or disables the alarm (64 hz) interrupt. f. enables or disables the alarm (512 hz) interrupt. g. enables or disables the alarm (8192 hz) interrupt. h. enables or disables the rtc interrupt. a ddress = (0xf003_0000) + (0x0200)
tmpa901cm tmpa901cm- 702 2010-07-29 11. rtcalmmis (rtc alm masked interrupt status register) bit bit symbol type reset value description [31:2] ? ? undefined read as undefined. [1] almint ro 0y0 alarm interrupt enabled status 0y0: interrupt not requested 0y1: interrupt requested [0] rtcint ro 0y0 rtc interrupt enabled status 0y0: interrupt not requested 0y1: interrupt requested a ddress = (0xf003_0000) + (0x0204) rtcalmmis rtcalmintctr xxxris (raw interrupt)
tmpa901cm tmpa901cm- 703 2010-07-29 z notes: (1) the rtc count-up control register always count s up. the 32 bit counter of rtc can?t be stopped. (2) after power-on, the rtccomp and rtcprst registers are undefined. so the rtccomp and rtcprst registers must be confined, and confirm the right data, can be read from the rtcdata register, then can set interrupt to enable state. if the rtccomp, rtcprst and other rtc relation registers are undefined state, don?t set mcu to the pcm mode. unexpected action resume from pcm maybe happen. please pay attention to it. (3) the rtcdata value is updated after the dvcc1a power supply is resumed by pcm releasing and the approximately one second elapsed. therefore, do not display time or use time data until one second elapses after the power supply is resumed. (4) the melody and alarm voltage circuitry are built in dvcc1a power supply, however rtc voltage circuitry is built in dvcc1b power supply.
tmpa901cm tmpa901cm- 704 2010-07-29 3.22 analog/digital converter a 10-bit serial conversion analog/digital conv erter (ad converter) having four channels of analog input is built in. figure 3.22.1 shows the block diagram of the ad converter. the four channels of analog input pins (an4 to an7) are used also as input dedi cat ed ports d (pd4 to pd7). note 1: to reduce the power supply current by pcm mode, the standby state may be maintained with the internal comparator still being enabled, depending on the timing. che ck that the ad converter operation is in a stop before executing mode switching. note 2: setting admod1 = 0 while the ad converter is in a stop can reduce current consumption. figure 3.22.1 block diagram of ad converter a d monitoring function interrupt a dcmint top-priority ad conversion end interrupt (adchpint) normal ad conversion end interrupt (adcnint) comparator vrefh vrefl sampling hold admod1 scan re p eat busy end start + ? internal data bus channel select control circuit ad conversion result register adreg4l to 7l adreg4h to 7h d/a converter normal ad conversion control circuit admod0 admod2 admod3 top-priority ad conversion control end compare register ad monitoring function control busy ad start control admod4 a ds itm vref hpadce start an7 (pd7) an6 (pd6) an5 (pd5) an4 (pd4) compare circuit top-priority ad conversion ? result register adregsph/l internal data bus multiplexer dacon ads ints[8]
tmpa901cm tmpa901cm- 705 2010-07-29 3.22.1 description of registers the following lists the sfrs: register name address (base+) description ? 0x0000 reserved ? 0x0004 reserved ? 0x0008 reserved ? 0x000c reserved ? 0x0010 reserved ? 0x0014 reserved ? 0x0018 reserved ? 0x001c reserved adreg4l 0x0020 a/d conversion resu lt lower-order register 4 adreg4h 0x0024 a/d conversion result higher-order register 4 adreg5l 0x0028 a/d conversion resu lt lower-order register 5 adreg5h 0x002c a/d conversion result higher-order register 5 adreg6l 0x0030 a/d conversion resu lt lower-order register 6 adreg6h 0x0034 a/d conversion result higher-order register 6 adreg7l 0x0038 a/d conversion resu lt lower-order register 7 adreg7h 0x003c a/d conversion result higher-order register 7 adregspl 0x0040 top-priority a/d conv ersion result lower-order register adregsph 0x0044 top-priority a/d conv ersion result higher-order register adcomregl 0x0048 a/d conversion result comparison lower-order register adcomregh 0x004c a/d conversion result comparison lower-order register admod0 0x0050 a/d mode control register 0 admod1 0x0054 a/d mode control register 1 admod2 0x0058 a/d mode control register 2 admod3 0x005c a/d mode control register 3 admod4 0x0060 a/d mode control register 4 ? 0x0064 reserved ? 0x0068 reserved ? 0x006c reserved adclk 0x0070 a/d conversion clock setting register adie 0x0074 a/d interrupt enable register adis 0x0078 a/d interrupt status register adic 0x007c a/d interrupt clear register ? 0x0080 reserved ? : reserved ? 0x0fff reserved note: notes for description of registers r/w: read/write possible ro: readable / write not reflected wo: writable / 0 can be read when read base address = 0xf008_0000
tmpa901cm tmpa901cm- 706 2010-07-29 3.22.1.1 control registers the a/d conver t er is controlled by the a/d mode control registers (admod0, admod1, admod2, admod3, and admod4). a/d conversion results are stored in the four registers of a/d conversion result higher-order/lower-order registers adreg4h/l to adreg7h/l. top-priority conversion results are stored in adregsph/l. ? admod register 1. admod0 (ad mode control register 0) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. normal ad conversion end flag read: 0y0: before conversion or being converted 0y1: end [7] eocfn (note) ro 0y0 write: invalid normal ad conversion busy flag read: 0y0: conversion stop ? 0y1: being converted [6] adbfn ro 0y0 write: invalid [5] ? ro 0y0 always read as 0 when read. [4] ? r/w 0y0 always write as 0 [3] itm r/w 0y0 the a/d conversion interrupt during channel fix and repeat conversion mode. itm 0y0: generates an interrupt per one conversion 0y1: reserved [2] repeat r/w 0y0 specifies repeat mode. 0y0: single conversion mode 0y1: repeat conversion mode [1] scan r/w 0y0 specifies scan mode. 0y0: channel fix mode 0y1: channel scan mode [0] ads r/w 0y0 a/d conversion start 0y0: don?t care 0y1: start conversion always read as 0 when read. r/w : read/write ro : read only wo : write only note: as read this register, is clear to 0. [description] a. they are the normal ad conversion end flag. 0y0: before conversion or being converted 0y1: end a ddress = (0xf008_0000) + (0x0050)
tmpa901cm tmpa901cm- 707 2010-07-29 b. they are the normal ad conversion busy flag. 0y0: conversion stop 0y1: being converted c. the a/d conversion interrupt during channel fix and repeat conversion mode. 0y0: generates an interrupt per one conversion 0y1: reserved d. selects the repeat mode. 0y0: single conversion mode 0y1: repeat conversion mode e. selects the scan mode. 0y0: channel fix mode 0y1: channel scan mode f. selects the a/d conversion start mode. 0y0: don?t care 0y1: start conversion mode always read as 0 when read.
tmpa901cm tmpa901cm- 708 2010-07-29 2. admod1 (ad mode control register 1) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7] dacon r/w 0y0 vref application control 0y0: off 0y1: on [6] ? ro 0y0 always read as 0 when read. [5] adscn r/w 0y0 operation mode setting during channel scan 0y0: 4-ch scan 0y1: reserved [4:3] ? r/w 0y00 always write as 0. analog input channel select scan 0 1 adscn 0/1 0 1 0y000 reserved reserved reserved 0y001 reserved reserved reserved 0y010 reserved reserved reserved 0y011 reserved reserved reserved 0y100 an4 an4 reserved 0y101 an5 an4 to an5 reserved 0y110 an6 an4 to an6 reserved adch [2:0] 0y111 an7 an4 to an7 reserved [2:0] adch[2:0] r/w 0y000 ? r/w : read/write ro : read only wo : write only note 1: to start ad conversion, be sure to write 1 in the admod1, and then wait for 3 s, which is the time taken until the internal reference voltage is stabi lized, and then write 1 in the admod0. note 2: to switch to standby mode after ad conversion end, set 0 in the admod1. [description] a. controls the vref application. 0y0: off 0y1: on b. sets the operation mode during channel scan. 0y0: 4-ch scan 0y1: reserved a ddress = (0xf008_0000) + (0x0054)
tmpa901cm tmpa901cm- 709 2010-07-29 c. selects analog input channels. scan 0 1 adscn 0/1 0 1 0y000 reserved reserved reserved 0y001 reserved reserved reserved 0y010 reserved reserved reserved 0y011 reserved reserved reserved 0y100 an4 an4 reserved 0y101 an5 an4 to 5 reserved 0y110 an6 an4 to 6 reserved adch [2:0] 0y111 an7 an4 to 7 reserved
tmpa901cm tmpa901cm- 710 2010-07-29 3. admod2 (ad mode control register 2) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. top-priority ad conversion end flag read: 0y0: before conversion or being converted 0y1: end [7] eocfhp(note) ro 0y0 write: invalid top-priority ad conversion busy flag read: 0y0: conversion stop 0y1: being converted [6] adbfhp ro 0y0 write: invalid [5] hpadce r/w 0y0 top-priority ad conversion start 0y0: don't care 0y1: conversion start. always read as 0 when read. [4:3] ? r/w 0y00 always write as 0. [2:0] hpadch[2:0] r/w 0y000 analog input channel select during top-priority conversion 0y100: an4, 0y110: an6 0y101: an5, 0y111: an7, other: reserved r/w : read/write ro : read only wo : write only note: as read this register, is clear to 0. [description] a. used to set the top-priority ad conversion end flag. 0y0: before conversion or being converted 0y1: end b. used to set the top-priority ad conversion busy flag. 0y0: conversion stop 0y1: being converted c. controls the start of top-priority ad conversion. 0y0: don't care 0y1: conversion start note: always read as 0 when read. d. analog input channel select during top-priority conversion 0y100: an4 0y110: an6 0y101: an5 0y111: an7 other: reserved a ddress = (0xf008_0000) + (0x0058)
tmpa901cm tmpa901cm- 711 2010-07-29 4. admod3 (ad mode control register 3) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7] ? r/w 0y0 always write as 0. [6] ? ro 0y0 always read as 0 when read. [5] adobic r/w 0y0 ad monitoring function interrupt setting 0y0: smaller than the comparison register settings 0y1: greater than the comparison register settings [4:1] regs[3:0] r/w 0y0000 bit to select the ad conversion result storage register to be compared with the settings of the comparison register during when the ad monitoring function is enabled regs[3:0] 0y0000: reserved 0y0001: reserved 0y0010: reserved 0y0011: reserved 0y0100: adreg4 0y0101: adreg5 0y0110: adreg6 0y0111: adreg7 0y1xxx: adregsp [0] adobsv r/w 0y0 ad monitoring function 0y0: disable 0y1: enable r/w : read/write ro : read only wo : write only [description] a. sets the ad monitoring function interrupt. 0y0: smaller than the comparison register settings 0y1: greater than the comparison register settings b. selects the ad conversion result storage register to be compared with the settings of the comparison register during when the ad monitoring function is enabled. 0y0000: reserved 0y0001: reserved 0y0010: reserved 0y0011: reserved 0y0100: adreg4 0y0101: adreg5 0y0110: adreg6 0y0111: adreg7 0y1xxx: adregsp c. controls the ad monitoring function. 0y0: disable 0y1: enable a ddress = (0xf008_0000) + (0x005c)
tmpa901cm tmpa901cm- 712 2010-07-29 5. admod4 (ad mode control register 4) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7] ? r/w 0y0 always write as 0. [6] ? r/w 0y0 always write as 0. [5] ? r/w 0y0 always write as 0. [4] ? r/w 0y0 always write as 0. [3:2] ? ro 0y00 always read as 0 when read. [1:0] adrst[1:0] r/w 0y00 resets the adc software by the write of 0y10 0y01. initializes all except the (adclk) register. r/w : read/write ro : read only wo : write only [description] a. resets the adc software by the write of 0y10 0y01. initializes all except the adclk register. a ddress = (0xf008_0000) + (0x0060)
tmpa901cm tmpa901cm- 713 2010-07-29 ? ad conversion result register. a/d conversion results are stored in the four registers of a/d conversion result higher-order/lower-order registers adreg4h/l to adreg7h/l. top-priority conversion results are stored in adregsph/l. since these registers are structured the same, adreg4 that is the conversion result storage register for the 4 channel is shown below: 1. adreg4l (ad conversion resu lt lower-order register 4 bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. [7] adr41 ro 0y0 ad conversion result lower-order bit 1 [6] adr40 ro 0y0 ad conversion result lower-order bit 0 [5:2] ? ro 0y0000 always read as 0 when read. [1] ovr4 ro 0y0 overrun flag 0y0: no overrun occurred 0y1: overrun occurred [0] adr4rf ro 0y0 ad conversion result storage flag 0y0: no change result 0y1: with conversion result [description] a. they are ad conversion result lower-order bits 1 to 0. b. used for the overrun flag. 0y0: no overrun occurred 0y1: overrun occurred c. used for the ad conversion result storage flag. 0y0: no change result 0y1: with conversion result note : as adreg4l to adreg7l and adregspl register s are the same composition. explain register adreg4l only, the other registers are same as adreg4l. about the address of adreg4l to adreg7l and a dregspl register, please check register map. a ddress = (0xf008_0000) + (0x0020)
tmpa901cm tmpa901cm- 714 2010-07-29 2. adreg4h (ad conversion resu lt higher-order register 4)) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. [7] adr49 ro 0y0 ad conversion result higher-order bit 9 [6] adr48 ro 0y0 ad conversion result higher-order bit 8 [5] adr47 ro 0y0 ad conversion result higher-order bit 7 [4] adr46 ro 0y0 ad conversion result higher-order bit 6 [3] adr45 ro 0y0 ad conversion result higher-order bit 5 [2] adr44 ro 0y0 ad conversion result higher-order bit 4 [1] adr43 ro 0y0 ad conversion result higher-order bit 3 [0] adr42 ro 0y0 ad conversion result higher-order bit 2 ? 9 8 76543210 conversion setting of channel x ? ? ? ? ? ? ? ? ? ? 7 6543210 ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? [description] a. they are ad conversion result higher-order bits 9 to 2. note : as adreg4h to adreg7h and adregsph register s are the same composition. explain register adreg4h only, the other registers are same as adreg4h. about the address of adreg4h to adreg7h and a dregsph register, please check register map. a dregxh adregxl ? always read as 0 when bits 5 to 2 are read. ? bit 0 is the ad conversion result storage flag . set to 1 when ad conversion settings are stored. cleared to 0 when the lower-order register (adregxl) is read. ? bit 1 is the overrun flag . set to 1 when conversion results are overwritten before reading the both conversion result storage registers (adregxh, adregxl). cleared to 0 by flag read. a ddress = (0xf008_0000) + (0x0024)
tmpa901cm tmpa901cm- 715 2010-07-29 ? ad conversion result comparison register 1. adcomregl (a/d conversion result comparison lower-order register) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7:6] adrcom[1:0] r/w 0y00 ad conversion result comparison lower-order bit 1 to 0 [5:0] ? ro 0y00000 always read as 0 when read. [description] a. they are ad conversion result comparison lower-order bits 1 to 0. 2. adcomregh (a/d conversion result comparison higher-order register) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7] adrcom9 r/w 0y0 ad conversion result comparison higher-order bit 9 [6] adrcom8 r/w 0y0 ad conversion result comparison higher-order bit 8 [5] adrcom7 r/w 0y0 ad conversion result comparison higher-order bit 7 [4] adrcom6 r/w 0y0 ad conversion result comparison higher-order bit 6 [3] adrcom5 r/w 0y0 ad conversion result comparison higher-order bit 5 [2] adrcom4 r/w 0y0 ad conversion result comparison higher-order bit 4 [1] adrcom3 r/w 0y0 ad conversion result comparison higher-order bit 3 [0] adrcom2 r/w 0y0 ad conversion result comparison higher-order bit 2 note: when setting or changing values in this r egister, keep the ad moni toring function disabled (admod3 = 0). [description] a. they are ad conversion result comparison higher-order bits 9 to 2. a ddress = (0xf008_0000) + (0x0048) a ddress = (0xf008_0000) + (0x004c)
tmpa901cm tmpa901cm- 716 2010-07-29 ? ad conversion clock setting register 1. adclk (ad conversion clock setting register) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7] ? r/w 0y1 always write as 1. [6:4] ? r/w 0y000 always write as 0. [3] ? ro 0y0 always read as 0 when read. [2:0] adclk[2:0] r/w 0y000 ad prescaler output select ad conversion 1-clock period = 0y000: pclk 0y001: pclk/2 0y010: pclk/4 0y011: pclk/8 0y1xx: pclk/16 note 1: while ad conversion is executed with a clock select ed in the register above, at this time, a conversion clock needs to be selected so that the ad conversion clock c an be 33 mhz or less in order to meet the guaranteed accuracy. note 2: during ad conversion, do not switch the conversion clock. [description] a. selects the ad prescaler output. ad conversion 1-clock period = 0y000: pclk 0y001: pclk/2 0y010: pclk/4 0y011: pclk/8 0y1xx: pclk/16 a ddress = (0xf008_0000) + (0x0070)
tmpa901cm tmpa901cm- 717 2010-07-29 pclk adclk ad conversion speed 0y00x ? setting disabled 100mhz 0y010 (pclk/4) 25mhz 1.84 sec 0y00x ? setting disabled 96mhz 0y010 (pclk/4) 24mhz 1.92 sec ad conversion speed can be determi ned with the following formula. conversion speed = 46 (1/adclk) note: in the period of ad conversion, don?t change the clock of adclk . 1 2 4 8 16 pclk adclk [2:0] conversion clock adclk
tmpa901cm tmpa901cm- 718 2010-07-29 ? interrupt register 1. adie (a/d interrupt enable register) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7:3] ? ro 0y00000 always read as 0 when read. [2] mie r/w 0y0 ad monitoring interrupt enable 0y0: disable 0y1: enable [1] hpie r/w 0y0 top-priority ad conversion interrupt enable 0y0: disable 0y1: enable [0] nie r/w 0y0 normal ad conversion interrupt enable 0y0: disable 0y1: enable note: please set neither top-priority ad conversion interr upt nor normal ad conversion interrupt at the same time. [description] a. controls the ad monitoring interrupt. 0y0: disable 0y1: enable b. controls the top-priority ad conversion interrupt. 0y0: disable 0y1: enable c. controls the normal ad conversion interrupt. 0y0: disable 0y1: enable a ddress = (0xf008_0000) + (0x0074)
tmpa901cm tmpa901cm- 719 2010-07-29 2. adis (ad interrupt status register) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. [7:3] ? ro 0y00000 always read as 0 when read. [2] mis ro 0y0 status of before masking an ad monitoring interrupt 0y0: no 0y1: interrupt occurred [1] hpis ro 0y0 status of before masking a top-priority ad conversion interrupt 0y0: no 0y1: interrupt occurred [0] nis ro 0y0 status of before masking a normal ad conversion interrupt 0y0: no 0y1: interrupt occurred [description] a. they are the status of before mask ing an ad monitoring interrupt. 0y0: no 0y1: interrupt occurred b. they are the status of before masking a top-priority ad conversion interrupt. 0y0: no 0y1: interrupt occurred c. they are the status of before masking a normal ad conversion interrupt. 0y0: no 0y1: interrupt occurred a ddress = (0xf008_0000) + (0x0078)
tmpa901cm tmpa901cm- 720 2010-07-29 3. adic (ad interrupt clear register) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7:3] ? ro 0y00000 always read as 0 when read. [2] mic wo 0y0 ad monitoring interrupt clear 0y0: ? 0y1: clear [1] hpic wo 0y0 top-priority ad conversion interrupt clear 0y0: ? 0y1: clear [0] nic wo 0y0 normal ad conversion interrupt clear 0y0: ? 0y1: clear [description] a. controls the ad monitoring interrupt. 0y0: ? 0y1: clear b. controls the top-priority ad conversion interrupt. 0y0: ? 0y1: clear c. controls the normal ad conversion interrupt. 0y0: ? 0y1: clear a ddress = (0xf008_0000) + (0x007c) ad conversion end interrupt adcint normal ad conversion end interrupt adcnint top-priority ad conversion end interrupt adchpint ad monitor interrupt adcmint
tmpa901cm tmpa901cm- 721 2010-07-29 3.22.2 description of operation 3.22.2.1 analog reference voltage apply the analog refe rence voltage's ?h? level side to the vrefh pin and the ?l? level side to the vrefl pin. writing 0 in the admod1 can turn off the switch for vrefh - vrefl. to start ad conversion, be sure to write 1 in the dacon, and then wait for 3 s, which is the time taken until the internal reference voltage is stabilized, and then write 1 in the admod0. 3.22.2.2 selecting analog input channels selecting an analog inpu t chann el depends on the operation mode of the ad converter. (1) for normal ad conversion when using an analog input channel in fix mode, select one channel from the an4 to an7 pins by setting (admod0 = 0) admod1. when using an analog input channel in scan mode, select one scan mode from the four scan modes by setting (admod0 = 1) admod1 . (2) for top-priority ad conversion select one channel from the analog input pins an4 to an7 by setting admod2. after reset, admod0 is initialized to 0 and admod1 to 0y000. since these settings are used for channel selection, the channel fixed input with the an0 pin will be selected. pins not used as analog input channels can be used as normal ports.
tmpa901cm tmpa901cm- 722 2010-07-29 3.22.2.3 ad conversion start the ad conversion has the two types of normal a d conv ersion and top-priority ad conversion. normal ad conversion can be started up by setting admod0 to 1. top-priority ad conversion can be started up by soft ware by setting admod2 to 1. for normal ad conversion, one operation mode is selected from the four types of operation modes specified by admod0. the operation mode for top-priority ad conversion is only single conversion by channel fix mode. when normal ad conversion is started, the ad conversion busy flag (admod0) that shows the state fo r ad being converted is set to 1. when top-priority ad conversion is started, the ad conversion busy flag (admod2) that shows the state for ad being converted is set to 1. in addition, when top-priority conversion is started during normal ad conversion, admod0 is kept to 1. and are set to 1 after conversion is completed. this flag is cleared to 0 only when read. two type ad conversion can be used. during normal ad conversion is executing, top-priority ad conversion can be carried out first. when admod2 is set to 1 during normal ad conversion, top-priority ad conversion's startup, normal ad conversi on being converted currently is cancelled immediately. then, top-priority ad conversion is started, starting the ad conversion (channel fix single conversion) for the channel specified by admod2. when this result is stored into adregsph/l, normal ad conversion is restarted from the cancelled channel. but during top-priority ad conversion, can?t set top-conversion ad conversion again. if top-priority ad conversion need to be set again, have to check that top-priority ad conversion being converted currently is end (ad conversion end flag: admod). then top-priority conversion ad conversion can be started.
tmpa901cm tmpa901cm- 723 2010-07-29 3.22.2.4 ad conversion modes and ad conversion end interrupt for ad conversion, the foll ow ing four operation modes are provided: for normal ad conversion, selection is available by setting admod0. as for top-priority ad conversion, only single conversion mode by channel fix mode is available. a. channel-fix single conversion mode b. channel-scan single conversion mode c. channel-fix repeat conversion mode d. channel-scan repeat conversion mode (1) normal ad conversion to select operation modes, use admod0. after ad conversion is started, admod0 is set to 1. when a specified ad conversion ends, the normal ad conversion end interrupt is ge nerated, admod0 is set 1 , shows the end of the ad conversion sequence. a. channel-fix single conversion mode setting admod0 to 0y00 selects the channel-fix single conversion mode. this mode performs a conversion only one time at one channel selected. after conversion ends, admod0 is set to 1, generating normal ad conversion end interrupt request. is cleared to 0 only by being read. b. channel-scan single conversion mode setting admod0 to 0y01 selects the channel-scan single conversion mode. this mode performs a conversion only one time at each scan channel selected. after scan conversion ends, admod0 is set to 1, generating normal ad conversion end interrupt request. is cleared to 0 only by being read. c. channel-fix repeat conversion mode setting admod0 to 0y10 selects the channel-fix repeat conversion mode. this mode performs a conversion at one channel selected repeatedly. after conversion ends, admod0 is set to 1. the timing of normal ad conversion end interrupt request generati on can be selected by setting admod0 . the timing of being set is also linked to the interrupt timing. admod0 is cleared to 0 only by being read. setting to 0 generates an interrupt request each time an ad conversion ends. in this case, conversion results are always stored into the storage register of adregxh/l. at the point of storage, is set to 1.
tmpa901cm tmpa901cm- 724 2010-07-29 d. channel-scan repeat conversion mode setting admod0 to 0y11 selects the channel-scan repeat conversion mode. this mode performs a conversion at select ed scan channels repeatedly. each time after the conversion at a final channel ends, admod0 is set to 1, generating normal ad conversion end in terrupt request. is cleared to 0 only by being read. to stop the repeat conversion mode (mode of c and d) operation, write 0 in admod1 . at the point when a scan conversion being executed ends, the repeat conversion mode ends. (2) top-priority ad conversion the operation mode is only single conversion by channel fix mode. the settings in admod0 are not involved. when startup conditions are established, a conversion at a channel specified by admod2 is performed only one time. when conversion ends, the top-priority ad conversion end interrupt is generated, which sets 1 in admod2. the eocfhp flag is cleared to 0 only by being read. table 3.22.1 relationship between ad conversion mode, interrupt generation timing, and flag operation admod0 conversion mode interrupt generation timing eocfn set timing (note) itm repeat scan channel fix single conversion after conversion end after conversion end ? 0 0 channel fix repeat conversion per one conversion each time after one conversion ends 0 1 0 channel scan single conversion after scan conversion end after scan conversion end ? 0 1 channel scan repeat conversion each time after one scan conversion ends each time after one scan conversion ends ? 1 1 note: eocfn is cleared to 0 only by being read.
tmpa901cm tmpa901cm- 725 2010-07-29 3.22.2.5 top-priority conversion mode top-priority ad c o nversion can be performed by interrupting into normal ad conversion. top-priority ad conversion can be started up by software while setting admod2 to 1 when top-priority ad conversion is started up during normal ad conversion, the ad conversion being converted currently is cancelled immediately to execute the single conversion at a channel specified by admod2. the conversion result is stored into adregsph/l, generating a top-priority ad conversion interrupt. after that, conversion is restarted from the channel where normal ad conversion was cancelled. note that a top-priority ad conversion started up during another top-priority ad conversion is ignored. example: ? when an7 top-priority ad conversion is started up with admod2 = 0y111 during repeat scan conversion at channels an4 to an6 with admod0 = 0y11 and admod1 = 0y0110 3.22.2.6 ad monitoring function sett ing admod3 to 1 enables the ad monitoring function. the value of result storage register that is appointed by admod3 is compared with the value of ad conversion result register (h/l), admod3 can select greater or smaller of comparison format. as register adie is enable, this comparison op eration is performed each time when a result is stored in the corresponding co nversion result stor age register. when conditions are met, the interrupt is generated. be careful that the storage registers assigned for the ad monitoring function are usually not ready by software, which means that the overrun flag is always set and the conversion result storage flag is also set. 3.22.2.7 ad conversion time one a d conversion takes 46 clocks in clud ing sampling clocks. the ad conversion clock is selected from 1/1, 1/2, 1/4, 1/8 pclk by . to meet the guaranteed accuracy, the ad conversion cloc k needs to be set from 0.625mhz to 33 mhz, or equivalently from 1.39 s to 73.6 s of ad conversion time. an4 an5 an6 an7 an6 an4 an5 top-priority ad conversion start conversion channel an6 conversion canceled an7 conversion started an6 re-conversion started
tmpa901cm tmpa901cm- 726 2010-07-29 3.22.2.8 storage and read of ad conversion results a/d conversion resu l ts are stored in the a/d conversion result higher-order/lower-order registers (adreg4h/l to adrg7h/l) for the normal ad conversion (adreg4h/l to adreg7h/l are read-only registers) ad conversion results of channels an4, an5, an6 and an7 are each stored into adreg4h/l, adreg5h/l, adreg6h/l, and adreg7h/l. table 3.22.2 shows the correspondence be tween analog input channels and ad conversion result registers. table 3.22.2 correspond ence between analog input channels and ad conversion result registers a nalog input channel (port d) ad conversion result register an4 adreg4h/l an5 adreg5h/l an6 adreg6h/l an7 adreg7h/l note: in order to detect overruns without omission, read the conversion result storage register 's higher-order bits first, and then read the lower-order bits next. as this result, receiving the result of ovrn = 0 and adrnrf = 1 for overruns existing in the lower-order bits means that a correct conversion result has been obtained. 3.22.2.9 data polling to process ad conversio n results by using data polling without using interrupts, perform a polling on admod0. after confirming that admod0 is set to 1, read the ad conversion storage register.
tmpa901cm tmpa901cm- 727 2010-07-29 3.23 watchdog timer (wdt) (runaway detection timer) the tmpa901cm contains a watchdog ti mer (wdt) for runaway detection. the watchdog timer is provided for detecting a cpu malfunction (runaway) due to causes such as noise and for restoring the cpu to a no rmal state. when the watchdog timer detects a runaway condition, it generates an interrupt to notify the interrupt controller and cpu of this condition. (interrupt source signal to interrupt controller: ints [0]) by connecting the watchdog timer output to the internal reset pin, a reset can be forcefully generated. ?????? note: please set to disable the wdt in debug operation. 3.23.1 block diagram wdt pclk apb bus control register wdt counter ints [0] wdt reset wdt ints [0] apb bus interrupt controller system reset wdt reset
tmpa901cm tmpa901cm- 728 2010-07-29 3.23.2 register functions the following lists the sfrs: register name address (base +) description wdogload 0x0000 watchdog load register wdogvalue 0x0004 the current value for the watchdog counter wdogcontrol 0x0008 watchdog control register wdogintclr 0x000c clears the watchdog interrupt wdogris 0x0010 watchdog raw interrupt status wdogmis 0x0014 watchdog masked interrupt status wdoglock 0x0c00 watchdog lock register base address = 0xf001_0000
tmpa901cm tmpa901cm- 729 2010-07-29 1. wdogload (watchdog load register) bit bit symbol type reset value description [31:0] wdtcnt r/w 0xffffffff wdt counter setting value 0x00000001 to 0xffffffff [description] a. specifies the value to be set to the wdt 32 bit counter (the clock of wdt counter is pclk). after wdogcontrol is enabled, the value set in wdogload is loaded into the internal decrement counter. the value of counter can be set from 0x00000001 to 0xffffffff. (0 can?t be set) when reading this register, the setting value is read out. 2. wdogvalue (the current value for the watchdog counter) bit bit symbol type reset value description [31:0] cwdtcnt ro 0xffffffff current value of the wdt counter [description] a. this bit can be read the current value of watch dog counter. a ddress = (0xf001_0000) + (0x0000) a ddress = (0xf001_0000) + (0x0004)
tmpa901cm tmpa901cm- 730 2010-07-29 3. wdogcontrol (watchdog control register) bit bit symbol type reset value description [31:2] ? ? undefined read as undefined. write as zero. [1] resen r/w 0y0 wdt reset output enable 0y0: disable 0y1: enable [0] inten r/w 0y0 wdt counter and interrupt enable 0y0: disable 0y1: enable [description] a. controls the wdt reset output. time until releasing reset is after pclk 5 clocks. b. 0y1: enables the wdt counter and the wdt interrupt. when this bit is set to 1, the value set in the wdogload register is loaded into the wdt counter and the counter starts decrementing. 4. wdogintclr (clears the watchdog interrupt) bit bit symbol type reset value description [31:0] wdtintclr wo undefined wdt interrupt clear (writing any value clears the interrupt.) [description] a. writing any value to this register clears the wdt interrupt and loads the value set in the wdogload register into the wdt counter. a ddress = (0xf001_0000) + (0x0008) a ddress = (0xf001_0000) + (0x000c)
tmpa901cm tmpa901cm- 731 2010-07-29 5. wdogris (watchdog raw interrupt status) bit bit symbol type reset value description [31:1] ? ? undefined read as undefined. [0] rawwdtint ro 0y0 wdt interrupt raw status 0y0: no interrupt 0y1: interrupt requested [description] a. indicates the raw status of the wdt interrupt. the value is anded with the interrupt enable signal (wdogcon trol) to generate an interrupt (wdogmis). 6. wdogmis (watchdog masked interrupt status) bit bit symbol type reset value description [31:1] ? ? undefined read as undefined. [0] wdtint ro 0y0 wdt interrupt enabled status 0y0: no interrupt 0y1: interrupt requested [description] a. this bit is status bit of the interrupt from wdt counter. the and value of wdogris and wdogcontrol is read out. a ddress = (0xf001_0000) + (0x0010) a ddress = (0xf001_0000) + (0x0014)
tmpa901cm tmpa901cm- 732 2010-07-29 7. wdoglock (watchdog lock register) ? ? bit bit symbol type reset value description [31:0] regwen wo undefined enables /disables writes to other wdt registers. 0x1acce551: enable others: disable (initial value: enable)? ? ? ? bit bit symbol type reset value description [31:1] reserved ? undefined read as undefined. [0] regwenst ro 0y0 indicates the enabled/disabled status of writes to other wdt registers. 0y0: enabled (not locked) 0y1: disabled (locked) [description] a. disables writes to other wdt registers to prevent the wdt registers from being inadvertently rewritten by runaway of program, etc. write except 0x1acce551: disabled writes to wdt register except this register. write 0x1acce551: enabled writes to wdt register except this register. b. indicates the enabled/disabled (not locked/locked) status of writes to other wdt registers. a ddress = (0xf001_0000) + (0x0c00) a ddress = (0xf001_0000) + (0x0c00)
tmpa901cm tmpa901cm- 733 2010-07-29 3.24 pmc (power management circuit) this product contains a power management ci rcuit that manages standby currents against current leaks from microprocessing products. the following eight systems of power supply are conceivable: ? 3.3-v power supply for a/d converters (for a/d converters: avcc3ad & avss3ad) ? 3.3-v digital power supply (for general pins : dvcc3io & dvsscom (note) ) ? 3.3-v and 1.8-v power supplies for memory (for memory control: dvccm & dvsscom) ? 3.3-v power supply for usb device (for usb device control: avdd3t/c & avss3t/c) ? 3.3-v power supply for usb host (for usb host control: avcc3h) ? 1.5-v-a internal power supply (for general circuits: dvcc1a & dvsscom) ? 1.5-v-b internal power supply (for rtc and pmc: dvcc1b & dvsscom) ? 1.5-v-c power supply for oscillators (for high frequency oscillators and pll: dvcc1c & dvss1c) note: the power of low frequency oscillator (xt1,xt2) is 3.3-v digital power . each power supply is independent. (vss is partially common.) in the power-cut mode, power supplies to most part of the internal circuits are cut off externally to reduce the leak current in a standby state. at this time, the state of each external pin can be fixed as ?h output?, ?l output?, ?high-z? or ?input?. (see the backup register output data register list later in this section). of the eight power supplies, those that should be supplied in the pcm state are dvcc3io, dvccm, avcc3ad, and dvcc1b. the power supplies that should be cut off are dvcc1a, dvcc1c, avdd3t, avdd3c and avcc3h. even if these power supplies are cut off after the tmpa901cm enters the pcm state, no floating current will be generated in the tmpa901cm. ? figure 3.24.1 state transition diagram of tmpa901cm reset (f osch /1) release of reset pll-off state (f osch /gear value) interrupt command interrupt command request for release halt state (cpu stops.) command pll-off state ((6 or 8) f osch / gear value) pcm state (part of power supplies are on) reset on command pcm(power cut mode)
tmpa901cm tmpa901cm- 734 2010-07-29 3.24.1 power supply system ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 3.24.2 power supply system cpu, other logic & ram 32kb i/o pad pmc rtc adc usb device high- osc a vcc3t a vcc3c avcc3ad dvcc3io dvccm low- osc dvcc1b dvss1c avss3ad dvsscom avss3t/c xt1 xt2 int, port, ? others dvcc1c ddp ddm x1 x2 a n4 to an7 dvcc1a usb host a vcc3h hdp hdm dvsscom
tmpa901cm tmpa901cm- 735 2010-07-29 3.24.2 example of connection and system application figure 3.24.3 example of power supply system figure 3.24.3 shows an example of the ext ernal circuit using this system. the pow e r management pin (pwe) controls the power supply to circuits and pins. in normal states including system reset, the pw e pin outputs ?high? to supply power to all blocks. in the power cut mode, the pwe pin outputs ?low? to cut off the power to most part of the internal circuits including the cpu, high-frequency oscillators, and usb power supply for reducing current consumption. the power cut mode is released by a wake-up request. then, the pwe pin outputs ?high? again to supply power to the internal circuits. rtc pmc xt1 xt2 i/o cpu other logic high_osc regulator 1.5v dvcc1a dvcc1c a vcc3ad avss3ad dvss1c dvsscom dvcc1b i/o power supply (5 types) external interrupt int9, a, b (tsi is also supported.) intkey sw en power supply management signal pwe main power sw en adc regulator 3.3v sw en delay circuit resetn power on reset circuit 0 s 1 usb device a vdd3t/c avss3t/c sw en usb host a vdd3h sw en dvsscom hdp hdm
tmpa901cm tmpa901cm- 736 2010-07-29 3.24.3 pmc registers composition to cut the current in power cut mode, pmc regi sters in next table (address (0xf002_0200 to 0xf002_041c)) composition is designed as below figure. there are different pmc setting registers in power off area (a1, a2, a3, a4) and power on area (b1) to realize power cut mode. and have to set the pmcwv1 register to renew the backup registers setting in power on area. f s hclk hclk hclk pmcwv1 register (a2) pmcrf1 register (a4) pmc relation registers(a1) ( write onl y) pins renew the setting of registers end flag of register renewing hclk apb i/f power on area in pcm mode backup register (b1) timing adjustment circuits pmc relation registers(a3) ( read onl y)
tmpa901cm tmpa901cm- 737 2010-07-29 3.24.4 description of operation the following shows a flowchart for entering and exiting the pcm state. figure 3.24.4 flowchart for enteri ng and exiting the pcm state execute the program in internal ram remove impediments to transit to pcm set the backup registers in the pmc as required select a wakeup trigger stop pll operation set warm-up time stop internal cache clear pcm release request enter pcm wait nop = 20? wakeup requested? ? ? release pcm state pcm select boot mode and multi mode resume normal operation yes no yes no
tmpa901cm tmpa901cm- 738 2010-07-29 3.24.4.1 entering the pcm state in the power cut mode, pow e r supplies to the internal circuits including the cpu are cut off. to enter the power cut mode, the following procedure must be observed to prepare for operation after exiting the power cut mode, to define the external pin states during the power cut mode, and to ensure proper mode transition. 1. execution procedure (1) program execution area for entering the pcm state, the program must be executing in the internal ram. (2) remove possible impediments to transition to the pcm mode before entering the pcm mode, stop all functions that may interfere with the mode transition operation. a. disable interrupts b. stop the watchdog timer (the watchdog timer is initially stopped.) c. stop the ad converter. d. stop dma operation ? stop the lcd controller. ? disable the sdram auto refresh function (so that the self refresh mode is enabled.) ? stop dma transfer. (3) set the pin states set the backup registers to fix the state of each pin during the pcm state. in the pcm state, the port states are controlled by the backup registers in the pmc. pc2 should be set as the pwe pin. only the cke pin (which is controlled by sdram) allows the pin state on exiting the pcm ? state to be different from the pin state after system reset. for details, refer to 3.24.4.3. (4) set th e wakeup conditions set the exter nal p in for waking up from the pcm state. the enable register, edge selection register and wakeup interrupt flag register are provided for each external pin. the internal rtc, an external key or an external interrupt can be selected as a wakeup trigger. (interrupts no t used can be masked.) to use pd6 as the tsi interrupt pin (inta), the debounce circuit must be disabled. for details, refer to the chapter on the tsi. (5) stop ofd operation stop the ofd circuit operation
tmpa901cm tmpa901cm- 739 2010-07-29 (6) stop pll operation. stop the pll circuit operation by setting high frequency clock to f osch. (7) set the warm-up time: pmcctl the external pwe pin changes from ?0? to ?1? approximately 1.5 xt1 (48s) after the wake-up interrupt. then, after a specified warm-up period and an additional interval of approximately 1 xt 1 (32s), the internal reset signal is released. since power stabilization time depends on the response of the power source to be used and conditions on the system, determine the warm-up time in consideration of the period required until power is stabilized. (the warm-up time can be selected in the range of 15.625 ms to 125 ms.) (8) disable the internal cache memory. (9) clear the wake-up request signals in the pmc before entering the power cut mode, the wake-up request signals in the pmc circuit must be cleared. (10) set the relevant pmc registers, and th en set the corresponding bits in the pmcwv1 register to enable the newly set values. (11) ? whether or not the values in each pmc register for which the corresponding bit in the pmcwv1 register is enabled have been copied into the backup register can be checked by reading the pmcrf1 register. (12) enable the power cut mode (pmcctl = ?1?) note: it is not possible to set pmcctl to ?0y1? and to change the settings of other bits in the same register (, , ) si multaneously. , and should be set while = ?0y0?. do not cha nge the values of these bits when writing ?0y1? to . (13) insert dummy instructions before transition to the power cut mode, approximately 7 xt1 (224s) note: programs to be started after warm-up either the built-in boot_rom or external memory (smccs0n) is selected and the program is started according to the settings of the external am0/1 pins a fter wakeup as in the case system reset is asserted. whether system reset starting or wakeup from the pc m state occurred can be known by checking the flag of pmcctl in the pmc circuit in the initial routine of the starting program. ? wakeup from the pcm state: pmcctl = 0y1 ? system reset starting: pmcctl = 0y0 in the startup program it is necessary to preapre a routine for checking pmcctl and branching program execution depending on the result.
tmpa901cm tmpa901cm- 740 2010-07-29 3.24.4.2 wakeup from pcm status an external interrupt is used to wake up f rom the power cut mode. whether a system reset or wake-up from th e power cut mode occurred can be known by checking the bit in the pmcctl register in the initial routine of the startup program. after wake-up from the power cut mode, either the internal boot rom or external memory (smccs0n) is selected according to the external am0 and am1 pins to start program execution. (it is prohibited to resume operation from a reset state while dvcc1a is cut off. before applying a reset, make sure that dvcc1a is stably powered. ) the interrupts that can be used to wake up from the power cut mode are rtc, resetn, int9, intb to inth, inta (tsi interrupt) and ki0 to ki3 interrupts. for details, refer to 3.26.5 ?pcm wake-up pins?. when a wake-up request is accepted, the pwe pin is set to ?1? and power is supplied to each block that has been placed in the power cut mode. after the warm-up time set in pmcctl< wutm1:0> has elapsed, hot_reset is automatically released. during the power cut mode, the state of each external pin remains unchanged. however, upon release of the internal hot_reset, all pins except the dmccke pin (note) are initialized to the system reset values. whether a system reset or wake-up from th e power cut mode occurred can be known by checking the bit in the pmcctl register in the initial routine of the startup program. * pmcctl in the pmc is not initialized at wake-up from the power cut mode. after wake-up, pmcctl should be cleared by using pmcres. the interrupt that triggered wake-up from th e power cut mode can be checked by using the bxxrint flags in the pmc. note: after a system reset, the dmccke pin is always initialized to the ?h? level. therefore, if sdram has been set to self-refresh mode before entering the power cut mode, the self-refresh mode will be cleared when the dmccke pin is initialized to the ?h? level after wake-up from the power cut mode. to avoid this situation, it is possible only for the dmccke pin, wh ich controls sdram, to specify di fferent pin levels after a system reset and after wake-up from the power cut mode. the dmccke pin level after wake-up from the power cut mode can be set in the relevant pmc register. dmccke pin status after system reset ?h? status after releasing pcm status if set to ?l? status; dmcckectl = 0y1 bsjoe = 0y1 bsjdata = 0y0
tmpa901cm tmpa901cm- 741 2010-07-29 3.24.4.3 status transitions before, during and after the power cut mode (pmc) transition under way pcm status powe r cut release under way normal status dvcc1a power on power off power on power on cpu, ram, etc reset stop reset restart operating melody / alarm circuit reset stop reset restart operating dvcc1b power on power on power on power on pmc circuit operating oper ating operating operating rtc circuit operating oper ating operating operating dvcc1c power on power off power on power on high-frequency oscillator operating stop restart operating dvcc3io power on power on power on power on pwe pin ?h? output ?l? output ?l h? output ?h? output low-frequency oscillator operating operating operating operating reset, am pin, etc. basic pins operating operating operating operating jtag pin pin fixed (port) pin fixed (pmc) reset restart operating nandf pin pin fixed (special function) pin fixed (pmc) reset restart operating keyout pin pin fixed (port) pin fixed (pmc) reset restart operating keyin pin input pin input pin input pin input pin i 2 c0 pin pin fixed (port) pin fixed (pmc) reset restart operating int pin pin fixed (port) pin fixed (pmc) reset restart operating uart0/1 pin pin fixed (port) pin fixed (pmc) reset restart operating spic0 pin pin fixed (port) pin fixed (pmc) reset restart operating i 2 s0/1 pin pin fixed (port) pin fixed (pmc) reset restart operating lcdc pin pin fixed (exclusive function) pin fixed (pmc) reset restart operating dvccm power on power on power on power on pins related to memory control pin fixed (exclusive function) pin fixed (pmc) reset restart operating dmccke pin pin fixed (exclusive function) pin fixed (pmc) pin fixed (pmc) software processing operating avcc3ad power on power on power on power on an4, an5, an7 pin input pin input pin input pin input pin an6 pin input pin pull-down (pmc) reset restart operating tsi pin pin fixed (port) pin fixed (pmc) reset restart operating avdd3t/c power on power off power on power on usb device pin operating stop reset restart operating avcc3h power on power off power on power on usb host pin operating stop reset restart operating note 1: the interrupt that triggered wake-up from the po wer cut mode can be checked by using the bxxrint flags in the pmc.
tmpa901cm tmpa901cm- 742 2010-07-29 note 2: after wake-up from the power cut mode, pmcct l remains ?1?. to enter the power cut mode again, pmcctl should be cleared by using pmcres. note 3: in the above table, ?pin fixed (pmc)? means that th e state of each external pin is controlled and fixed by the pmc even during the power cut mode. special control is required for some pins (pc2, sj6), as shown in the circuit diagram below. ? tmpa901cmxbg pc2 pwe gpo pcdata pmcctl dmccke bsjdata dmcckectl pins of px pmc circuit bpxdata pcm state (internal signal) except the initial value /pcm pins of sx exclusive pins bsxdata pcm sate (internal signal) pcm state pcm state nc nc gpiocfr1 gpiocfr2 (not use) initial value /pcm t a d b c gpioxfr1 gpioxfr2 the initial value /pcm except the initial value /pcm except the initial value /pcm selector selector selector selector selector selector sj6 dmccke dvcc1b dvcc1a and others power pmcctl initial value (high level)
tmpa901cm tmpa901cm- 743 2010-07-29 3.24.5 notes on operation power on/off sequence (initial power on/complete power off) for the initial power on, the internal power should be supplied first, and for the complete power off, the internal power should be cut off last. note 1: simultaneous rising and falling of the internal 1.5-v power and the external pin power is possible. however, the external pins may become unstable momentarily at that time. therefore, rising and falling of the external power should be made while the internal 1.5-v power is st able as shown by the thick line in the above figure if the devices connecting to the lsis in the surrounding parts can be affected. note 2: do not allow the 3.3-v power to rise earlier than the 1.5-v power. in the same way, do not allow the 3.3-v power to fall after the 1.5-v power. external pin power supply dvcc1a dvcc1b dvcc1c resetn avcc3ad dvcc3io dvccm power should rise within 100 ms. the 1.5-v power should fall after the 3.3-v power falls. the 3.3-v power should rise after the 1.5-v power rises. power should fall within 100 ms. high-frequency oscillator stabilize time + 20 system clocks 1.5-v internal power supply pwe pin pcm status power on power off usb power supply avdd3t/c avcc3h
tmpa901cm tmpa901cm- 744 2010-07-29 3.24.6 pcm status release pins the power-cut mode is reset on interrupt request. the table below shows the external pins for which the power-cut mode can be released. note:? when the pins in the table are not used, the power-cut mode can also be released on interrupt from the built-in rtc. port bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pa ki3 ki2 ki1 ki0 pc i2c0da int9 pd py intb px inta(inttsi)
tmpa901cm tmpa901cm- 745 2010-07-29 3.24.7 description of registers the following lists the sfrs: table 3.24.1 register list (1/3) register name address (base+) description bpadata 0x0900 porta data set register when power cut mode bpbdata 0x0904 portb data set register when power cut mode bpcdata 0x0908 portc data set register when power cut mode bpddata 0x090c portd data set register when power cut mode ? 0x0914 reserved ? 0x0918 reserved ? 0x0924 reserved ? 0x0928 reserved ? 0x092c reserved ? 0x0930 reserved bpndata 0x0934 portn data set register when power cut mode ? 0x0944 reserved bptdata 0x094c portt data set register when power cut mode bpudata 0x0950 portu data set register when power cut mode bpvdata 0x0954 portv data set register when power cut mode ? 0x0b80 reserved bpboe 0x0b84 portb data out enable control when power cut mode bpcoe 0x0b88 portc data out enable control when power cut mode bpdoe 0x0b8c portd data out enable control when power cut mode ? 0x0b90 reserved ? 0x0b94 reserved ? 0x0b98 reserved ? 0x0ba4 reserved ? 0x0ba8 reserved ? 0x0bac reserved ? 0x0bb0 reserved bpnoe 0x0bb4 portn data out enable control when power cut mode ? 0x0bc4 reserved bptoe 0x0bcc portt data out enable control when power cut mode bpuoe 0x0bd0 portu data out enable control when power cut mode bpvoe 0x0bd4 portv data out enable control when power cut mode base address = 0xf002_0000
tmpa901cm tmpa901cm- 746 2010-07-29 table 3.24.2 register list (2/3) register name address (base+) description bsadata 0x0800 sa data set register when power cut mode bsbdata 0x0804 sb data set register when power cut mode ? 0x0808 reserved ? 0x080c reserved bsedata 0x0810 se data set register when power cut mode bsfdata 0x0814 sf data set register when power cut mode bsgdata 0x0818 sg data set register when power cut mode bshdata 0x081c sh data set register when power cut mode bsjdata 0x0824 sj data set register when power cut mode bskdata 0x0828 sk data set register when power cut mode bsldata 0x082c sl data set register when power cut mode ? 0x084c reserved ? 0x0850 reserved bsaoe 0x0a80 sa data out enable control when power cut mode bsboe 0x0a84 sb data out enable control when power cut mode ? 0x0a88 reserved ? 0x0a8c reserved bseoe 0x0a90 se data out enable control when power cut mode bsfoe 0x0a94 sf data out enable control when power cut mode bsgoe 0x0a98 sg data out enable control when power cut mode bshoe 0x0a9c sh data out enable control when power cut mode bsjoe 0x0aa4 sj data out enable control when power cut mode bskoe 0x0aa8 sk data out enable control when power cut mode bsloe 0x0aac sl data out enable control when power cut mode ? 0x0acc reserved ? 0x0ad0 reserved bpaie 0x0d80 port a wakeup input enable bpcie 0x0d88 port c wakeup input enable bpdie 0x0d8c port d wakeup input enable ? 0x0d94 reserved ? 0x0db4 reserved ? 0x0dc4 reserved base address = 0xf002_0000
tmpa901cm tmpa901cm- 747 2010-07-29 table 3.24.3 register list (3/3) register name address (base+) description bparele 0x0200 porta enable register of wake-up trigger from power cut mode bpdrele 0x0204 portd enable register of wake-up trigger from power cut mode brtrele 0x0208 rtc request enable register of wake-up trigger from power cut mode bpxrele 0x020c others port enable register of wake-up trigger from power cut mode bpaedge 0x0220 porta selection register of wake-up trigger edge from power cut mode bpdedge 0x0224 portd selection register of wake-up trigger edge from power cut mode bpxedge 0x022c others ports selection register of wake-up trigger edge from power cut mode bparint 0x0240 porta wake-up interrupt status register bpdrint 0x0244 portd wake-up interrupt status register brtrint 0x0248 rtc wake-up interrupt status register bpxrint 0x024c others ports wale- up interrupt status register pmcdrv 0x0260 external port driverbility control register dmcckectl 0x0280 dmccke pin setting register (pcm mode) pmcctl 0x0300 power management circuit control register pmcwv1 0x0400 renew control for pmc registers - 0x0408 reserved pmcres 0x041c flag clear register for pmcctl_r base address = 0xf002_0000
tmpa901cm tmpa901cm- 748 2010-07-29 table 3.24.4 backup register output data register list 1 register address correspond to port register name type bit7 bit6 bit5 bit4 bit3 bit2 bit1 0bit 0xf002_0900 pa bpadata note1) w ? ? ? ? bpadata3 bpadata2 bpadata1 bpadata0 0xf002_0904 pb bpbdata w ? ? ? ? bpbdata3 bpbdata2 bpbdata1 bpbdata0 0xf002_0908 pc bpcdata w bpcdata7 bpcdata6 ? bpcdata4 bpcdata3 ? ? ? 0xf002_090c pd bpddata w read as undefined. write as zero. 0xf002_0914 ? reserved w ? ? ? ? ? ? ? ? 0xf002_0918 ? reserved w ? ? ? ? ? ? ? ? 0xf002_0924 ? reserved w ? ? ? ? ? ? ? ? 0xf002_0928 ? reserved w ? ? ? ? ? ? ? ? 0xf002_092c ? reserved w ? ? ? ? ? ? ? ? 0xf002_0930 ? reserved w ? ? ? ? ? ? ? ? 0xf002_0934 pn bpndata w ? ? ? ? ? ? bpndata1 bpndata0 0xf002_0944 ? reserved w ? ? ? ? ? ? ? ? 0xf002_094c pt bptdata w bptdata7 bptdata6 bptdata5 bptdata4 bptdata3 bptdata2 bptdata1 bptdata0 0xf002_0950 pu bpudata w bpudata7 bpudata6 bpudata5 bpudata4 bpudata3 bpudata2 bpudata1 bpudata0 0xf002_0954 pv bpvdata w bpvdata7 bpvdata6 bpvdata5 bpvdata4 bpvdata3 bpvdata2 bpvdata1 bpvdata0 these registers define the output data in the power cut mode. each register is initialized to ?0? after reset, and retains the previous value after hot reset. ? register bit value = 0y0: ?l? output register bit value = 0y1: ?h? output note1: in the power cut mode, the bpadata register is init ialized to 0x00 and the internal pull-up circuit of port a is turned off. to continue using the pull- up circuit of port a, bpadata must be set to 0xff before entering the power cut mode..
tmpa901cm tmpa901cm- 749 2010-07-29 table 3.24.5 backup register output enable register list 1 register address correspond to port register name type bit7 bit6 bit5 bit4 bit3 bit2 bit1 0bit 0xf002_0b80 pa reserved ? D read as undefined. write as zero. 0xf002_0b84 pb bpboe w D bpboe3 bpboe2 bpboe1 bpboe0 0xf002_0b88 pc bpcoe w bpcoe7 bpcoe6 D bpcoe4 bpcoe3 D D D 0xf002_0b8c pd bpdoe w bpd oe7 bpdoe6 bpdoe5 bpdoe4 D 0xf002_0b94 pf bpfoe w D 0xf002_0b98 pg bpgoe w D 0xf002_0ba4 pj bpjoe w D 0xf002_0ba8 pk bpkoe w D 0xf002_0bac pl bploe w D 0xf002_0bb0 pm bpmoe w D 0xf002_0bb4 pn bpnoe w D bpnoe1 bpnoe0 0xf002_0bc4 pr bproe w D 0xf002_0bcc pt bptoe w bptoe7 bptoe6 bptoe5 bptoe4 bptoe3 bptoe2 bptoe1 bptoe0 0xf002_0bd0 pu bpuoe w bpuoe7 bpuoe6 bpu oe5 bpuoe4 bpuoe3 bpuoe2 bpuoe1 bpuoe0 0xf002_0bd4 pv bpvoe w bpvoe7 bpvoe6 bpvoe5 bpvoe4 bpvoe3 bpvoe2 bpvoe1 bpvoe0 these registers enable or disable data output in the power cut mode. each register is initialized to ?0? after reset, and retains the previous value after hot reset. ?? register bit value = 0y0: disable output register bit value = 01y: enable output
tmpa901cm tmpa901cm- 750 2010-07-29 note: when using a touch screen function at portd, t he bpdoe and the bpddata setting are shown belows. ? input enable pd7 avcc3ad gpiod bpdoe ?? input enable pd6 avcc3ad avss3ad 50k gpiod bpdoe ?? bpddata ?? input enable pd5 avss3ad gpiod bpdoe ?? ain5 input enable pd4 avss3ad gpiod bpdoe ?? ain4
tmpa901cm tmpa901cm- 751 2010-07-29 table 3.24.6 backup register output data register list 2 register address correspond to port register name type bit7 bit6 bit5 bit4 bit3 bit2 bit1 0bit 0xf002_0800 sa bsadata w bsadata7 bsadata6 bsadata5 bsadata4 bsadata3 bsadata2 bsadata1 bsadata0 0xf002_0804 sb bsbdata w bsbdata7 bsbdata6 bsbdata5 bsbdata4 bsbdata3 bsbdata2 bsbdata1 bsbdata0 0xf002_0808 D reserved w 0xf002_080c D reserved w 0xf002_0810 se bsedata w bsedata7 bsedata6 bsedata5 bsedata4 bsedata3 bsedata2 bsedata1 bsedata0 0xf002_0814 sf bsfdata w bsfdata7 bsfdata6 bsfdata5 bsfdata4 bsfdata3 bsfdata2 bsfdata1 bsfdata0 0xf002_0818 sg bsgdata w bsgdata7 bsgdata6 bsgdata5 bsgdata4 bsgdata3 bsgdata2 bsgdata1 bsgdata0 0xf002_081c sh bshdata w bshdata7 D D bshdata4 bshdata3 bshdata2 D D 0xf002_0824 sj bsjdata w D bsjdata6 bsjdata5 bsjdata4 bsjdata3 bsjdata2 bsjdata1 bsjdata0 0xf002_0828 sk bskdata w D D bskdata5 bskdata4 D D bskdata1 bskdata0 0xf002_082c sl bsldata w D note bsldata5 bsldata4 D bsldata2 bsldata1 bsldata0 0xf002_084c D reserved w 0xf002_0850 D reserved w these registers define the output data in the power cut mode. each register is initialized to ?0? after reset, and retains the previous value after hot reset. register bit value = 0y0: ?l? output register bit value = 0y1: ?h? output note: read as undefined.
tmpa901cm tmpa901cm- 752 2010-07-29 table 3.24.7 backup register output enable register list 2 register address correspond to port register name type bit7 bit6 bit5 bit4 bit3 bit2 bit1 0bit 0xf002_0a80 sa bsaoe w bsaoe7 bsaoe6 bsaoe5 bsaoe4 bsaoe3 bsaoe2 bsaoe1 bsaoe0 0xf002_0a84 sb bsboe w bsboe7 bsboe6 bsboe5 bsboe4 bsboe3 bsboe2 bsboe1 bsboe0 0xf002_0a88 D r e s e r v e d w 0xf002_0a8c D r e s e r v e d w 0xf002_0a90 se bseoe w bseoe7 bseoe6 bseoe5 bseoe4 bseoe3 bseoe2 bseoe1 bseoe0 0xf002_0a94 sf bsfoe w bsfoe7 bsfoe6 bsf oe5 bsfoe4 bsfoe3 bsfoe2 bsfoe1 bsfoe0 0xf002_0a98 sg bsgoe w bsgoe7 bsgoe6 bsgoe5 bsgoe4 bsgoe3 bsgoe2 bsgoe1 bsgoe0 0xf002_0a9c sh bshoe w bshoe7 D D bshoe4 bshoe3 bshoe2 D D 0xf002_0aa4 sj bsjoe w D bsjoe6 bsjoe5 bsjoe4 bsj oe3 bsjoe2 bsjoe1 bsjoe0 0xf002_0aa8 sk bskoe w bskoe5 bskoe4 bskoe1 bskoe0 0xf002_0aac sl bsloe w D note bsloe5 bsloe4 D bsloe2 bsloe1 bsloe0 0xf002_0acc D reserved w 0xf002_0ad0 D r e s e r v e d w these registers enable or disable data output in the power cut mode. each register is initialized to ?0? after reset, and retains the previous value after hot reset. ?? register bit value = 0y0: enable output register bit value = 01y: disable output note: read as undefined.
tmpa901cm tmpa901cm- 753 2010-07-29 1. bparele register bit bit symbol type reset value hot reset value description [31:4] ? ? undefined undefined read as undefined. write as zero. [3] bparele3 r/w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable [2] bparele2 r/w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable [1] bparele1 r/w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable [0] bparele0 r/w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable [description] a. enable pcm release request of key input ki [3:0]. note: when an enable setting is required, bpaie[3:0] regi ster bit also need to set to be an enable similarly. 2. bpdrele register bit bit symbol type reset value hot reset value description [31:8] ? ? undefined undefined read as undefined. write as zero. [7] ? ? undefined undefined read as undefined. write as zero. [6] bpdrele6 r/w 0y0 hold eve dat a pcm release request enable 0y0: disable 0y1: enable [5:0] ? ? undefined undefined read as undefined. write as zero. [description] a. enable pcm release request of inta (inttsi). note: when an enable setting is required, bpdie[6]register bit also need to set to be an enable similarly. a ddress = (0xf002_0000) + (0x0200) a ddress = (0xf002_0000) + (0x0204)
tmpa901cm tmpa901cm- 754 2010-07-29 3. brtrele register bit bit symbol type reset value hot reset value description [31:1] ? ? undefined undefined read as undefined. write as zero. [0] brtrele0 r/w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable [description] a. enable pcm release request of rtc. 4. bpxrele register bit bit symbol type reset value hot reset value description [31:8] ? ? undefined undefined read as undefined. write as zero. [7:2] reserved r/w 0y0 hold eve data read as undefined. write as zero. [1] pd7intb r/w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable [0] pc7int9 r/w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable ( eh) a. < pd7intb> enable pcm release request of pd7(intb). note: when an enable setting is required, bpdie[7]register bit also need to set to be an enable similarly. b. < pc7int9> enable pcm release re quest of pc7(int9) . note: when an enable setting is required, bpcie[7]register bit also need to set to be an enable similarly. a ddress = (0xf002_0000) + (0x0208) a ddress = (0xf002_0000) + 0x020c
tmpa901cm tmpa901cm- 755 2010-07-29 5. bpaedge register bit bit symbol type reset value hot reset value description [31:4] ? ? undefined undefined read as undefined. write as zero. [3] bpaedge3 r/w 0y0 hold eve data edge selection of pcm release request 0y0 : rise edge 0y1 : fall edge [2] bpaedge2 r/w 0y0 hold eve data edge selection of pcm release request 0y0 : rise edge 0y1 : fall edge [1] bpaedge1 r/w 0y0 hold eve data edge selection of pcm release request 0y0 : rise edge 0y1 : fall edge [0] bpaedge0 r/w 0y0 hold eve data edge selection of pcm release request 0y0 : rise edge 0y1 : fall edge [description] a. edge selection of pcm release request of key input ki [3:0]. 6. bpdedge register bit bit symbol type reset value hot reset value description [31:8] ? ? undefined undefined read as undefined. write as zero. [7] ? ? undefined undefined read as undefined. write as zero. [6] bpdedge6 r/w 0y0 hold eve data edge selection of pcm release request 0y0: rise edge 0y1: fall edge [5:0] ? ? undefined undefined read as undefined. write as zero. [description] a. edge selection of pcm release request of inta (inttsi). a ddress = (0xf002_0000) + (0x0220) a ddress = (0xf002_0000) + (0x0224)
tmpa901cm tmpa901cm- 756 2010-07-29 7. bpxedge register bit bit symbol type reset value hot reset value description [31:8] ? ? undefined undefined read as undefined. write as zero. [7:2] reserved ? undefined undefined read as undefined. write as zero. [1] bpxedgeb [0] bpxedge9 r/w 0y0 ?` edge selection of pcm release request 0y0: rise edge 0y1: fall edge a. edge selection of pcm release request of intb. b. edge selection of pcm release request of int9. a ddress = (0xf002_0000) + 0x022c
tmpa901cm tmpa901cm- 757 2010-07-29 8. bparint register bit bit symbol type reset value hot reset value description [31:4] ? ? undefined undefined read as undefined. write as zero. [3] bparint3 r/w undefined hold eve data pcm release interrupt status write: 0y0: clear 0y1: reserved read: 0y0: no interrupt request 0y1: interrupt request [2] bparint2 r/w undefined hold eve data pcm release interrupt status write: 0y0: clear 0y1: reserved read: 0y0: no interrupt request 0y1: interrupt request [1] bparint1 r/w undefined hold eve data pcm release interrupt status write: 0y0: clear 0y1: reserved read: 0y0: no interrupt request 0y1: interrupt request [0] bparint0 r/w undefined hold eve data pcm release interrupt status write: 0y0: clear 0y1: reserved read: 0y0: no interrupt request 0y1: interrupt request [description] a. pcm release interrupt status of key input ki [3:0]. write: 0y0: clear 0y1: reserved read: 0y0: no interrupt request 0y1: interrupt request for the factor of pcm release can be confirmed. please write this register bit as 0 before entering pcm status. a ddress = (0xf002_0000) + (0x0240)
tmpa901cm tmpa901cm- 758 2010-07-29 9. bpdrint register bit bit symbol type reset value hot reset value description [31:7] ? ? undefined undefined read as undefined. write as zero. [6] bpdrint6 r/w undefined hold eve data pcm release interrupt status write: 0y0: clear 0y1: reserved read: 0y0: no interrupt request 0y1: interrupt request [5:0] ? ? undefined undefined read as undefined. write as zero. [description] a. pcm release interrupt status of inta (inttsi). write: 0y0: clear 0y1: reserved read: 0y0: no interrupt request 0y1: interrupt request for the factor of pcm release can be confirmed. please write this register bit as 0 before entering pcm status. a ddress = (0xf002_0000) + (0x0244)
tmpa901cm tmpa901cm- 759 2010-07-29 10. brtrint register bit bit symbol type reset value hot reset value description [31:1] ? ? undefined undefined read as undefined. write as zero. [0] brtrint0 r/w undefined hold eve data pcm release interrupt status write: 0y0: clear 0y1: reserved read: 0y0: no interrupt request 0y1: interrupt request [description] a. pcm release interrupt status of rtc. write: 0y0: clear 0y1: reserved read: 0y0: no interrupt request 0y1: interrupt request for the factor of pcm release can be confirmed. please write this register bit as 0 before entering pcm status. a ddress = (0xf002_0000) + (0x0248)
tmpa901cm tmpa901cm- 760 2010-07-29 11. bpxrint register bit bit symbol type reset value hot reset value description [31:8] ? ? undefined undefined read as undefined. write as zero. [7:2] reserved ? undefined undefined read as undefined. write as zero. [1] pd7intb r/w undefined hold eve data pcm release interrupt status write: 0y0: clear 0y1: reserved read: 0y0: no interrupt request 0y1: interrupt request [0] pc7int9 r/w undefined hold eve data pcm release interrupt status write: 0y0: clear 0y1: reserved read: 0y0: no interrupt request 0y1: interrupt request [description] a. pcm release interrupt status of intb. b. pcm release interrupt status of int9. write: 0y0: clear 0y1: reserved read: 0y0: no interrupt request 0y1: interrupt request for the factor of pcm release can be confirmed. please write this register bit as 0 before entering pcm status. a ddress = (0xf002_0000) + 0x024c
tmpa901cm tmpa901cm- 761 2010-07-29 12. pmcdrv register bit bit symbol type reset value hot reset value description [31:5] ? ? undefined undefined read as undefined. write as zero. [4] drv_lcd r/w 0y1 hold eve data lcdc relation port drive power 0y0: 12 ma (1.8 v to 3.0 v) 0y1: 6 ma (3.0 v to 3.6 v) [3:2] ? ? undefined undefined read as undefined. write as zero. [1] drv_mem1 r/w 0y0 hold eve data [0] drv_mem0 r/w 0y1 hold eve data memory relation port drive power 0y00: reserved 0y01: 1/2 (3.3 v ? 0.3 v) 0y10: reserved 0y11: 1/1 (1.8 v ? 0.1 v) [description] a. < drv_lcd, drv_mem[1:0]> these bits can be used to change the drive capability of ports related to lcd and memory according to the voltage range to be used. 13. dmcckectl register bit bit symbol type reset value hot reset value description [31:1] ? ? undefined undefined read as undefined. write as zero. [0] dmcckehld r/w 0y0 hold eve data output selection of sj6 0y0: dmccke 0y1: pmc register setting [description] a. after a system reset, the dmccke pin is always initialized to the ?h? level. therefore, if sdram has been set to self-refre sh mode before entering the po wer cut mode, the self-refresh mode will be cleared when the dmccke pin is initialized to the ?h? level after wake-up from the power cut mode. to avoid this situation, it is possible only for the dmccke pin, which controls sdram, to specify different pin levels after a system reset and after wake-up from the power cut mode. the dmccke pin level after wake-up from the power cut mode can be set in the relevant pmc register. dmccke pin status after a system reset ?h? level after wake-up from power cut mode to set the dmccke pin to ?l? level: dmcckectl= 0y1 bsjoe= 0y1 bsjdata= 0y0 a ddress = (0xf002_0000) + (0x0260) a ddress = (0xf002_0000) + (0x0280)
tmpa901cm tmpa901cm- 762 2010-07-29 14. pmcctl register bit bit symbol type reset value hot reset value description [31:8] ? ? undefined undefined read as undefined. write as zero. [7] pcm_on note) r/w 0y0 hold eve data power cut enable 0y0: disable 0y1: enable [6] pmcpwe r/w 0y1 hold eve data output selection of pwe 0y0: port function (pc2) 0y1: pmc register output (pwe) [5:3] ? ? undefined undefined read as undefined. write as zero. [2] reserved ? undefined undefined read as undefined. write as zero. [1] wutm1 r/w 0y0 hold eve data [0] wutm0 r/w 0y0 hold eve data warm-up timing setting 0y00: 2 (15.625 ms) 0y01: 2 10 (31.25 ms) 0y10: 2 11 (62.5 ms) 0y11: 2 12 (125 ms) [description] a. the power cut mode is entered by writing ?1? to . note1: the power cut mode is etnered by writing ?1? to . at this time, and in the same register cannot be changed simultaneously. and should be set while =0. when writing ?1? to , do not change the values of and . note2: cannot be cleared by writing ?0?. to clear this bit, use the bit in the pmcres register. note3: the external pwe signal changes from ?0? to ?1? approximately 1.5 xt1 (48 s) after a wake-up request interrupt. then, after a specified warm-up period and an additional interval of approximately 1 xt1 (32 s), the internal reset signal is released. since power stabilization time depends on the response of the power source to be used and conditions on the system, determine the wa rm-up time in considerat ion of the period required until power is stabilized. a ddress = (0xf002_0000) + (0x0300)
tmpa901cm tmpa901cm- 763 2010-07-29 15. pmcwv1 register bit bit symbol type reset value hot reset value description [31:6] ? ? undefined undefined read as undefined. write as zero. [6] pmcbdtv w 0y0 hold eve data back-up register value update 0y0: do not update 0y1: update [5] pmcctlv r/w 0y0 hold eve data pmcctl register value update 0y0: do not update 0y1: update [4] dmcckectlv r/w 0y0 hold eve data dmcckectl register value update 0y0: do not update 0y1: update [3] pmcdrvv r/w 0y0 hold eve data pmcdrv register value update 0y0: do not update 0y1: update [2] bparintv r/w 0y0 hold eve data bparint register value update 0y0: do not update 0y1: update [1] bpaedgev r/w 0y0 hold eve data bpaedge register value update 0y0: do not update 0y1: update [0] bparelev r/w 0y0 hold eve data bparele register value update 0y0: do not update 0y1: update [description] there are different pmc setting registers in power off area and power on area to realize power cut mode. and have to set the pmcwv1 register to renew the backup registers setting in power on area. for how to control pmc registers, see ? 3.24.3 pmc registers composition a. , , and other registers 0y0: do not update when =0y0, values newly written to the appropriate register are not reflected in the corresponding backup register in the dvcc1b circuit. ????????? 0y1: update when =0y1, values newly written to the appropriate register are reflected in the corresponding backup register in the dvcc1b circuit. ? note: pmcctl is a special bit that cannot be updated by using the pmcwv1 register. use the pmcres register to update pmcctl. ??? a ddress = (0xf002_0000) + 0x0400
tmpa901cm tmpa901cm- 764 2010-07-29 16. pmcres register bit bit symbol type reset value hot reset value description [31:8] ? ? undefined undefined read as undefined. write as zero. [7] res_pcmon r/w 0y0 0y0 pmcctl clear 0y0: invalid 0y1: clear [6:0] ? ? undefined undefined read as undefined. write as zero. [description] a. by writing ?1? to , pmcctl can be cleared. this bit cannot be used for waking up from the power cut mode. 0y0: invalid 0y1: clear 17. bpaie register bit bit symbol type reset value hot reset value description [31:4] ? ? undefined undefined read as undefined. write as zero. [3] bpaie3 w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable [2] bpaie2 w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable [1] bpaie1 w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable [0] bpaie0 w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable [description] a. enable pcm release request of key input ki [3:0]. note: when an enable setting is required, bparele[3:0] regi ster bit also need to set to be an enable similarly. a ddress = (0xf002_0000) + 0x041c a ddress = (0xf002_0000) + 0x0d80
tmpa901cm tmpa901cm- 765 2010-07-29 18. bpcie register bit bit symbol type reset value hot reset value description [31:8] ? ? undefined undefined read as undefined. write as zero. [7] bpaie7 w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable [6:0] ? ? undefined undefined read as undefined. write as zero. [description] a. enable pcm release request of int9 . note: when an enable setting is required, bpxrele[0] regi ster bit also need to set to be an enable similarly. 19. bpdie register bit bit symbol type reset value hot reset value description [31:8] ? ? undefined undefined read as undefined. write as zero. [7] bpdie7 w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable [6] bpdie6 w 0y0 hold eve data pcm release request enable 0y0: disable 0y1: enable [5:0] ? ? undefined undefined read as undefined. write as zero. [description] a. enable pcm release request of pd7(intb) and pd6(inta) . note: when an enable setting is required, bpdrele[6] regi ster bit also need to set to be an enable similarly. note: when an enable setting is required, bpxrele[1] regi ster bit also need to set to be an enable similarly. a ddress = (0xf002_0000) + 0x0d88 a ddress = (0xf002_0000) + 0x0d8c
tmpa901cm tmpa901cm- 766 2010-07-29 3.24.8 program examples the program example shown below is written assuming that it is executed from the internal ram. before entering the power cut mode, stop all functions that may interfere with transition to the power cut mode and set the relevant pins as required. ? stop the watchdog timer. (the watchdog timer is stopped in the initial state.) ? stop the ad converter. ? stop dma operation. ? stop the lcd controller. ? stop the auto-refresh mode of sdram (change to the self-refresh mode). ? stop dma transfer. ? fix pin levels as required. at the same time as fixing pin levels, al so set the levels of the relevant pins during the power cut mode. for each external interrupt that can be used for waking up from the power cut mode, the active edge can be selected in the relevant register. to use the pd6 pin as inta (inttsi interrupt), it is necessary to disable the debounce circuit. ? disable interrupts. ? stop ofd operation. ? stop pll operation. ? disable the internal cache memory.
tmpa901cm tmpa901cm- 767 2010-07-29 ; ? example) wakeup from the power cut mode by using port a[0]. ;------------ back up data set register in power cut mode ldr r0,=bpadata ; port a pull-up enable for pmc mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bpbdata ; pb data set in power cut mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bpcdata ; pc data set in power cut mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bpddata ; pd data set in power cut mode mov r1,#0x00000040 str r1,[r0] ldr r0,=bpndata ; pn data set in power cut mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bptdata ; pt data set in power cut mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bpudata ; pu data set in power cut mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bpvdata ; pv data set in power cut mode mov r1,#0x000000ff str r1,[r0]
tmpa901cm tmpa901cm- 768 2010-07-29 ;------------ back up data output enable register ldr r0,=bpboe ; pb output enable mov r1,#0x000000ff str r1,[r0] ldr r0,=bpcoe ; pc output enable mov r1,#0x000000ff str r1,[r0] ldr r0,=bpdoe ; pd output enable mov r1,#0x000000f0 str r1,[r0] ldr r0,=bpnoe ; pn output enable mov r1,#0x000000ff str r1,[r0] ldr r0,=bptoe ; pt output enable mov r1,#0x000000ff str r1,[r0] ldr r0,=bpuoe ; pu output enable mov r1,#0x000000ff str r1,[r0] ldr r0,=bpvoe ; pv output enable mov r1,#0x000000ff str r1,[r0]
tmpa901cm tmpa901cm- 769 2010-07-29 ;------------ back up data set register in power cut mode ldr r0,=bsadata ; sa data set in power cut mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bsbdata ; sb data set in power cut mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bsedata ; se data set in power cut mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bsfdata ; sf data set in power cut mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bsgdata ; sg data set in power cut mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bshdata ; sh data set in power cut mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bsjdata ; sj data set in power cut mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bskdata ; sk data set in power cut mode mov r1,#0x000000ff str r1,[r0] ldr r0,=bsldata ; sl data set in power cut mode mov r1,#0x000000ff str r1,[r0]
tmpa901cm tmpa901cm- 770 2010-07-29 ;------------ back up data output enable register ldr r0,=bsaoe ; sa output enable mov r1,#0x000000ff str r1,[r0] ldr r0,=bsboe ; sb output enable mov r1,#0x000000ff str r1,[r0] ldr r0,=bseoe ; se output enable mov r1,#0x000000ff str r1,[r0] ldr r0,=bsfoe ; sf output enable mov r1,#0x000000ff str r1,[r0] ldr r0,=bsgoe ; sg output enable mov r1,#0x000000ff str r1,[r0] ldr r0,=bshoe ; sh output enable mov r1,#0x000000ff str r1,[r0] ldr r0,=bsjoe ; sj output enable mov r1,#0x000000ff str r1,[r0] ldr r0,=bskoe ; sk output enable mov r1,#0x000000ff str r1,[r0] ldr r0,=bsloe ; sl output enable mov r1,#0x000000ff str r1,[r0]
tmpa901cm tmpa901cm- 771 2010-07-29 ;------------ wake up enable register ldr r0,=bpaie ; pa0, set enable mov r1,#0x00000001 str r1,[r0] ldr r0,=bpcie ; disable mov r1,#0x00000000 str r1,[r0] ldr r0,=bpdie ; disable mov r1,#0x00000000 str r1,[r0] ;------------ wake up enable register ldr r0,=bparele ; pa0, set enable mov r1,#0x00000001 str r1,[r0] ldr r0,=bpdrele ; disable mov r1,#0x00000000 str r1,[r0] ldr r0,=brtrele ; disable mov r1,#0x00000000 str r1,[r0] ldr r0,=bpxrele ; disable mov r1,#0x00000000 str r1,[r0] ;------------ wake up source edge select register ldr r0,=bpaedge ; pa0, set rising edge mov r1,#0x00000000 str r1,[r0] ldr r0,=bpdedge ; mov r1,#0x00000000 str r1,[r0] ldr r0,=bpxedge ; mov r1,#0x00000000 str r1,[r0]
tmpa901cm tmpa901cm- 772 2010-07-29 ;------------ wake up source initial register ldr r0,=bparint ; clear th e status of wakeup request mov r1,#0x00000000 str r1,[r0] ldr r0,=bpdrint ; clear th e status of wakeup request mov r1,#0x00000000 str r1,[r0] ldr r0,=brtrint ; clear the status of wakeup request mov r1,#0x00000000 str r1,[r0] ldr r0,=bpxrint ; clear th e status of wakeup request mov r1,#0x00000000 str r1,[r0] ;------------ pre pmcctl register set ldr r0,=pmcctl ;pmcctl pre set mov r1,#0x00000043 str r1,[r0] ;------------ pmc write valid register ldr r0,=pmcwv1 ;pmcwv1 mov r1,#0x0000007f str r1,[r0] nop nop nop nop nop nop ;------------ write valid flag check wait_pmcwv1 ldr r0,=pmcwv1 ldr r0,[r0] and r0,#0x7f cmp r0,#0x7f bne wait_pmcwv1 nop nop ldr r0,=pmcctl ;pmcctl ;pmc mode mov r1,#0xc3 str r1,[r0] nop_loop nop nop nop nop b nop_loop halt ;
tmpa901cm tmpa901cm- 773 2010-07-29 3.25 usb host controller the usb host controller (usbhc) is compliant with the usb specification revision 2.0 and the open hci specification release 1.0a and support s usb transfers at 12 mbps (full-speed).the usbhc is connected to the multi layer bus system via on-chip sram. the usbhc is subject to some restrictions. for details, see section 3.25.8. 3.25.1 system overview the key features of the usbhc are as follows: (1) supports full-speed (12 mbps) usb devi ces. but not supports low-speed (1.5mbps) (2) supports control, bulk, interrupt and isochronous transfers. (3) contains two 16-byte fifo buffers (in and ou t) in the bus bridge logic for connecting with the cpu, allowing a maximum of 16-byte burst transfers. (4) supports data transfers between the fifo buffers in the bus bridge logic and the on-chip sram. 3.25.2 system configuration the usbhc consists of the following three blocks: (1) usbhc core (ohci) (2) usb transceiver (3) cpu bus bridge logic figure 3.25.1 usb host controller usbhc core usb transceiver hdp hdm usb transceiver usbpon usb vbus on signal overcurrent signal buffer on chip ram (internal ram-1: 8 kbyte) 0xf800_8000-0xf800_9fff ahb bus ahb bus ints [27] (intusb) usbocn bus bridge ahb slave i/f
tmpa901cm tmpa901cm- 774 2010-07-29 3.25.3 interrupts the usbhc generates the following interrupts: ? scheduling overrun ? hcdonehead write back ? start of frame ? resume detect ? unrecoverable error ? frame number overflow ? root hub status change ? ownership change when an event that causes an interrupt occurs, the usbhc sets the corresponding bit in the hcinterruptstatus register. at this time, if the masterinterruptenable (mie) bit is enabled and the corresponding bit in the hcinterruptenable register is enabled, a usb interrupt (intsub) is generated. the usbhc driver software can clear each bit in the hcinterruptstatus register by writing a 1 to it (the driver software cannot set these bits, and the usbhc cannot clear these bits).
tmpa901cm tmpa901cm- 775 2010-07-29 3.25.4 reset the usbhc is initialized by a hardware or software reset. 3.25.4.1 hardware reset a hardware reset is gene rated by the ext ern al reset pin or intern al reset(wdt reset, ofd reset, pcm release). ? all registers are initialized. ? the usbhc outputs the reset signal on the usb bus ? the usb state changes to the usbreset state. ? list processing and sof toke n generation are disabled. ? the framenumber field of the hcfmnumber register is not incremented. 3.25.4.2 software reset a software reset is generat e d when the hostcontrollerreset bit in the hccommandstatus register is set to 1. ? all ohci registers are initialized. the host controller driver does not modify the interruptrouting bit and the remotewakeupconnected bit in the hccontrol register. the hcbcr0 register is not initialized. ? the usbhc outputs the reset signal on the usb bus ? the usb state changes to the usbsuspend state. (the functionalstate bit in the hcc ontroller register is set to 0x03 (usbsuspend).) 3.25.5 bus power control the usbhc has a control signal for an external power ic for vbus. this signal is controlled by the usbpon pin (pt4). to use pt4 as the usbpon pin, the port t control register (ptfc) must be set appropriately. then, setting the lpsc bit in the hcrhstatus regi ster to 1 makes the usbpon pin output high level. the usbocn pin (pt5) is used to detect overcu rrent conditions. when low level is detected on this pin, the usbhc sets the oci bit in the ohci hcrhstatus register to 1. (to use pt5 as the usbocn pin, the port t control register (ptfc) must be set appropriately.)
tmpa901cm tmpa901cm- 776 2010-07-29 3.25.6 registers the usbhc contains a set of control registers compliant with the open hci specification (ohci) which are mapped into the memory space. the bus bridge logic for connecting with the cpu also includes control registers. these registers are directly accessible from the cpu via a 32-bit bus. ? table 3.25.1 registers compliant with the usb open hci specification ?????? note 1: the addresses listed in table 3.25.1 are those mapped on the cpu registers. note 2: the open hci s pecification release 1.0a spec ifies the frameremaining (fr) and frameremainingtoggle (frt) bits in the hcfmremaining register and the fram enumber (fn) bit in the hcfmnumber register as read-only to the host control driver (hcd). however, the usb 1.1 ohci host control core allows write accesses to these registers by hcd for debug purposes. if hcd writes to these registers, undefined results will be obtained. these bits must not be written by hcd. register name address (base+) description hcrevision 0x0000 hccontrol 0x0004 hccommandstatus 0x0008 hcinterruptstatus 0x000c hcinterruptenable 0x0010 hcinterruptdisable 0x0014 hchcca 0x0018 hcperiodcurrented 0x001c hccontrolheaded 0x0020 hccontrolcurrented 0x0024 hcbulkheaded 0x0028 hcbulkcurrented 0x002c hcdonehead 0x0030 hcfminterval 0x0034 hcfmremaining 0x0038 hcfmnumber 0x003c hcperiodstart 0x0040 hclsthreshold 0x0044 hcrhdescriptora 0x0048 hcrhdescripterb 0x004c hcrhstatus 0x0050 hcrhportstatus 0x0054 0x0058 0x005c hcbcr0 0x0080 base address= 0xf450_0000
tmpa901cm tmpa901cm- 777 2010-07-29 1. hcrevision register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol reserved read/write (hcd) read/write (hc) reset state 15 14 13 12 1110987654 3 2 10 bit symbol reserved rev read/write (hcd) r read/write (hc) r reset state 0 0 0 1 0 0 0 0 ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? bit mnemonic field name function [31:8] reserved [7:0] rev revision this read-only field contains the bcd representation of the version of the hci specification that is implemented by this hc. for example, a value of 0x11 corresponds to version 1.1. all of the hc implementations that are compliant with this specification will have a value of 0x10. a ddress = (0xf450_0000) + (0x0000)
tmpa901cm tmpa901cm- 778 2010-07-29 2. hccontrol register the hccontrol register defines the operating modes for the host controller. most of the fields in this register are modified only by the host controller driver, except hostcontrollerfunctionalstat e and remotewakeupconnected. ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol reserved read/write (hcd) read/write (hc) reset state 15 14 13 12 11109 87654 3 2 10 bit symbol reserved rwe rwc ir hcfs ble cle ie ple cbsr read/write (hcd) r/w read/write (hc) r r/w r r/w r r r r r reset state 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit ? mnemonic ? field name ? function ? [31:11] reserved [10] rwe remotewakeup enable this bit is used by hcd to enabl e or disable the remote wakeup feature upon the detection of upstr eam resume signaling. when this bit is set and the resumedetected bit in hcinterruptstatus is set, a remote wakeup is signaled to the host system. setting this bit has no impact on the generation of hardware interrupt. [9] rwc remotewakeup connected this bit indicates whether the hc supports remote wakeup signaling. if remote wakeup is supported and used by the system, it is the responsibility of system firmware to set this bit during (power on self test) post. the hc clears the bit upon a hardware reset but does not alter it upon a software reset. [8] ir interrupt routing this bit determines the routing of interrupts generated by events registered in hcinterruptstatus. if cl eared, all interrupts are routed to the normal host bus interrupt mechanism. if set, interrupts are routed to the system management interrupt. hcd clears this bit upon a hardware reset, but it does not alter this bit upon a software reset. hcd uses this bit as a tag to i ndicate the ownership of the hc. a ddress = (0xf450_0000) + (0x0004)
tmpa901cm tmpa901cm- 779 2010-07-29 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit ? mnemonic ? field name ? function ? [7:6] hcfs hostcontroller functionalstate forusb 00:usbreset 01:usbresume 10:usboperational 11:usbsuspend a transition to usboperational from another state causes sof generation to begin 1 ms later. hcd may determine whether the hc has begun sending sofs by reading t he startofframe field of the hcinterrupt register. this field may be changed by the hc only when in the usbsuspend state. the hc may move from the usbsuspend state to the usbresume state after detecting the resume signaling from a downstream port. the hc enters usbsuspend after a software reset, whereas it enters usbreset after a hardware reset. the latter also resets the root hub and asserts subsequent reset signaling to downstream ports. [5] ble bulklistenable this bit is set to enabl e the processing of the bulk list in the next frame. if cleared by hcd, processing of the bulk list does not occur after the next sof. the hc checks this bit whenever it determines to process the list. when disabled, hcd may modify t he list. if hcbulkcurrented is pointing to an ed to be removed, hcd must advance the pointer by updating hcbulkcurrented before re-enabling processing of the list. [4] cle controllist enable this bit is set to enable the processing of the control list in the next frame. if cleared by hcd, processing of the control list does not occur after the next sof. the hc must check this bit whenever it determines to process the list. when disabl ed, hcd may modify the list. if hccontrolcurrented is pointing to an ed to be removed, hcd must advance the pointer by updating hccontrolcurrented before re-enabling processing of the list. [3] ie isochronous enable this bit is used by hcd to enable/ disable processing of isochronous eds. while processing the periodic list in a frame, the hc checks the status of this bit when it finds an isochronous ed (f=1). if set (enabled), the hc continues processi ng the eds. if cleared (disabled), the hc halts processing the periodic list (which now contains only isochronous eds) and begins proce ssing the bulk and control lists. the setting of this bit is also valid in the next frame. * this product has some restri ctions on isochronous transfers. [2] ple periodiclist enable this bit is set to enable the processi ng of the periodic list in the next frame. if cleared by hcd, processing of the periodic list does not occur after the next sof. the hc must check this bit before it starts processing the list. [1:0] cbsr controlbulk serviceratio this bit specifies the service ratio between control and bulk eds. before processing any of the nonperiodic lists, the hc must compare the ratio specified with its internal count on how many nonempty control eds have been processed, in determining whether to continue serving another control ed or switch to bulk eds. the internal count will be retained when crossing the frame boundary. in case of a reset, hcd is responsible for restoring this value. cbsr no. of control eds over bulk eds served 00 1:1 01 2:1 10 3:1 11 4:1
tmpa901cm tmpa901cm- 780 2010-07-29 ? 3. hccommandstatus register the hccommandstatus register is used by the host controller to receive commands issued by the host controller driver, as well as reflecting the current status of the host controller. to the host controller driver, it ap pears to be a "write to set" register. the host controller must ensure that bits written as 1 become set in the register while bits written as 0 remain unchanged in the register. the host controller driver may issue multiple distinct commands to the host controller wi thout concern for corrupting previously issued commands. the host controller driver has normal read a ccess to all bits. the schedulingoverruncount field indicates the number of frames with which the host controller has detected the scheduling overrun error. this occurs when the periodic list does not complete before eof. when a sche duling overrun error is detected, the host controller increments the counter and sets the schedulingoverrun field in the hcinterruptstatus register. ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol reserved soc read/write (hcd) r read/write (hc) r/w reset state 0 0 15 14 13 12 1110987654 3 2 10 bit symbol reserved ocr blf clf hcr read/write (hcd) r/w read/write (hc) r/w reset state 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit mnemonic field name function [31:18] reserved [17:16] soc scheduling overruncount these bits are incremented at each scheduling overrun error. it is initialized to 00b and wraps around at 11b. this will be incremented when a scheduling overrun is detec ted even if schedulingoverrun in hcinterruptstatus has already been set. this is used by hcd to monitor any persistent scheduling problems. [15:4] reserved [3] ocr ownership changerequest this bit is set by the os hcd to request a change of hc control. when set, the hc will set the ownershipchange field in hcinterruptstatus. after the changeover, this bit is cleared and remains so until the next request is made from the os hcd. a ddress = (0xf450_0000) + (0x0008)
tmpa901cm tmpa901cm- 781 2010-07-29 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit mnemonic field name function [2] blf bulklistfilled this bit is used to indicate whether there are any tds on the bulk list. it is set by hcd whenever it adds a td to an ed in the bulk list. when the hc begins to process the head of the bulk list, it checks bf. as long as bulklistfilled is 0, the hc will not start processing the bulk list. if bulklistfilled is 1, the hc will start processing the bulk list and will set bf to 0. if the hc finds a td on the list, then the hc will set bulklistfilled to 1 causing the bulk list processing to continue. if no td is found on the bulk list, and if hcd does not set bulklistfilled, then bulklistfilled will still be 0 when the hc completes processing the bulk list and bulk list processing will stop. [1] clf controllistfilled this bit is used to i ndicate whether there are any tds on the control list. this is set by hcd whenever it adds a td to an ed in the control list. when the hc begins to process the head of the control list, it checks clf. as long as controllistfilled is 0, the hc will not start processing the control list. if cf is 1, the hc will start processing the control list and will set controllistfilled to 0. if the hc finds a td on the list, then the hc will set controllistfilled to 1 causing the control list processing to continue. if no td is found on the control list, and if hcd does not set controllistfilled, then controllistfilled will still be 0 when the hc completes processing the control list and control list processing will stop. [0] hcr hostcontroller reset this bit is set by hcd to initiate a software reset of the hc. regardless of the functional state of the hc, it moves to the usbsuspend state in which most of the operational registers are reset except those stated otherwise; e.g., the interruptrouting field of hccontrol, and no host bus accesses are allowed. this bit is cleared by the hc upon completion of the reset operation. the reset operation must be completed within 10 s. this bit, when set, should not cause a reset to the root hub and no subsequent reset signaling should be asserted to its downstream ports.
tmpa901cm tmpa901cm- 782 2010-07-29 4. hcinterruptstatus register this register provides status on various events that cause hardware interrupts. when an event occurs, the host controller sets the corresponding bit in this register. when a bit is set, a hardware interrupt is generated if the interrupt is enabled in the hcinterruptenable register and the masterinterruptenable bit is set. the host controller driver may clear specific bits in this register by writing 1 to bit positions to be cleared. the host controller driver may not set any of these bits. the host controller will never clear the bit. ? ? ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol rese rved oc reserved read/write (hcd) r/w read/write (hc) r/w reset state 0 15 14 13 12 1110987654 3 2 10 bit symbol reserved rhsc fno ue rd sf wdh so read/write (hcd) r/w read/write (hc) r/w reset state 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit mnemonic field name function [31] reserved [30] oc ownership change this bit is set by the hc when hcd sets the ownershipchangerequest field in hccommandstatus. this event, when unmasked, will always generate an system management interrupt (smi) immediately. this bit is tied to 0b when the smi pin is not implemented. [29:7] reserved [6] rhsc roothubstatus change this bit is set when the content of hc rhstatus or the content of any of hcrhportstatus[numberofdownstreamport] is changed. [5] fno framenumber overflow this bit is set when the msb of hcfmnumber (bit 15) changes value from 0 to 1 or from 1 to 0, and after hccaframenumber is updated. [4] ue unrecoverable error this bit is set when the hc detects a system error not related to usb. the hc should not proceed with any processing nor signaling before the system error is corrected. hcd clears this bit after the hc is reset. a ddress = (0xf450_0000) + (0x000c)
tmpa901cm tmpa901cm- 783 2010-07-29 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit mnemonic field name function [3] rd resumedetected this bit is set when the hc detects that a device on usb is asserting resume signaling. this is the trans ition from no resume signaling to resume signaling causing this bit to be set. this bit is not set when hcd sets the usbresume state. [2] sf startofframe this bit is set by the hc at each start of a frame and after the update of hccaframenumber. the hc also generates a sof token at the same time. [1] wdh writebackdone head this bit is set immediately after the hc writes hcdonehead to hccadonehead. further updates of the hccadonehead will not occur until this bit is cleared. hcd should only clear this bit after it saves the content of hccadonehead. [0] so scheduling overrun this bit is set when the usb schedule for the current frame overruns and after the update of hccaframenumber. a scheduling overrun will also cause the schedulingoverrunc ount of hccommandstatus to be incremented.
tmpa901cm tmpa901cm- 784 2010-07-29 5. hcinterruptenable register each enable bit in the hcinterruptenable regist er corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcint erruptenable register is used to control which events generate a hardware interrupt. when a bit is set in the hcinterruptstatus register and the corresponding bit in the hcinterruptenable register is set and the masterinterruptenable bit is set, then a hardware interrupt is requested on the host bus. writing a 1 to a bit in this register sets the corresponding bit, whereas writing a 0 to a bit in this register leaves the corresponding bit unchanged. on read, the current value of this register is returned. ? ? ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol mie oc reserved read/write (hcd) r/w read/write (hc) r reset state 0 0 15 14 13 12 1110987654 3 2 10 bit symbol reserved rhsc fno ue rd sf wdh so read/write (hcd) r/w read/write (hc) r reset state 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit mnemonic field name function [31] mie masterinterrupt enable a '0' written to this field is ignored by the hc. a '1' written to this field disables interrupt generation due to event s specified in the other bits of this register. this is used by hcd as a master interrupt enable. [30] oc ownership change 0: ignored 1: disables interrupt generation due to ownership change. [29:7] reserved [6] rhsc roothubstatus change 0: ignored 1: enables interrupt generation due to root hub status change. [5] fno framenumber overflow 0: ignored 1: enables interrupt generation d ue to frame number overflow. [4] ue unrecoverable error 0: ignored 1: enables interrupt generation due to unrecoverable error. [3] rd resumedetected 0: ignored 1: enables interrupt generation due to resume detect. [2] sf startofframe 0: ignored 1: enables interrupt generation due to start of frame. [1] wdh writebackdone head 0: ignored 1: enables interrupt generation due to hcdonehead writeback. [0] so scheduling overrun 0: ignored 1: enables interrupt generation due to scheduling overrun. a ddress = (0xf450_0000) + (0x0010)
tmpa901cm tmpa901cm- 785 2010-07-29 6. hcinterruptdisable register each disable bit in the hcinterruptdisable register corresponds to an associated interrupt bit in the hcinterruptstatus register . the hcinterruptdisable register is coupled with the hcinterruptenable register. thus, writing a 1 to a bit in this register clears the corresponding bit in the hcinterruptenable register, whereas writing a 0 to a bit in this register leaves the corresponding bit in the hcinterruptenable register unchanged. on read, the current value of the hcinterruptenable register is returned. ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol mie oc reserved read/write (hcd) r/w read/write (hc) r reset state 0 0 15 14 13 12 1110987654 3 2 10 bit symbol reserved rhsc fno ue rd sf wdh so read/write (hcd) r/w read/write (hc) r reset state 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit mnemonic field name function [31] mie masterinterrupt enable a '0' written to this field is ignored by the hc. a '1' written to this field disables interrupt generation due to ev ents specified in the other bits of this register. this field is set after a hardware or software reset. [30] oc ownership change 0: ignored 1: disables interrupt generation due to ownership change. [29:7] reserved [6] rhsc roothubstatus change 0: ignored 1: disables interrupt generation due to root hub status change. [5] fno framenumber overflow 0: ignored 1: disables interrupt generation due to frame number overflow. [4] ue unrecoverable error 0: ignored 1: disables interrupt generation due to unrecoverable error. [3] rd resumedetected 0: ignored 1: disables interrupt generation due to resume detect. [2] sf startofframe 0: ignored 1: disables interrupt generation due to start of frame. [1] wdh writebackdone head 0: ignored 1: disables interrupt generation due to hcdonehead writeback. [0] so scheduling overrun 0: ignored 1: disables interrupt generati on due to scheduling overrun. a ddress = (0xf450_0000) + (0x0014)
tmpa901cm tmpa901cm- 786 2010-07-29 7. hchcca register the hchcca register contains the physical address of the host controller communication area. the host controller driver determines the alignment restrictions by writing all ones to hchcca and reading the content of hchcca. the alignment is evaluated by examining the number of zeros in the lower order bits. the minimum alignment is 256 bytes. therefore, bits 0 through 7 always return 0 when read. this area is used to hold the control structures and the interrupt table that are accessed by both the host controller and the host controller driver. ? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol hcca read/write (hcd) r/w read/write (hc) r reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 1110987654 3 2 10 bit symbol hcca reserved read/write (hcd) r/w read/write (hc) r reset state 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit mnemonic field name function [31:8] hcca hostcontroller communication area this is the base address of the host controller communication area. [7:0] reserved a ddress = (0xf450_0000) + (0x0018)
tmpa901cm tmpa901cm- 787 2010-07-29 8. hcperiodcurrented register the hcperiodcurrented register contains the physical address of the current isochronous or interrupt endpoint descriptor. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol pced read/write (hcd) r read/write (hc) r/w reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 1110987654 3 2 10 bit symbol pced reserved read/write (hcd) r read/write (hc) r/w reset state 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit ? mnemonic ? field name ? function ? [31:4] pced periodcurrent ed this is used by the hc to point to the head of one of the periodic lists which will be processed in the current frame. the content of this register is updated by the hc after a periodic ed is processed. hcd may read the content in determining which ed is currently being processed at the time of reading. [3:0] reserved a ddress = (0xf450_0000) + (0x001c)
tmpa901cm tmpa901cm- 788 2010-07-29 9. hccontrolheaded register the hccontrolheaded register contains the physical address of the first endpoint descriptor of the control list. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol ched read/write (hcd) r/w read/write (hc) r reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 1110987654 3 2 10 bit symbol ched reserved read/write (hcd) r/w read/write (hc) r reset state 0 0 0 0 0 0 0 0 0 0 0 0 ? ? bit mnemonic field name function [31:4] ched controlheaded the hc traverses the control list starting with the hccontrolheaded pointer. the content is loaded from hcca during the initialization of the hc. [3:0] reserved a ddress = (0xf450_0000) + (0x0020)
tmpa901cm tmpa901cm- 789 2010-07-29 10. hccontrolcurrented register the hccontrolcurrented register contains the physical address of the current endpoint descriptor of the control list. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol cced read/write (hcd) r/w read/write (hc) r/w reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 1110987654 3 2 10 bit symbol cced reserved read/write (hcd) r/w read/write (hc) r/w reset state 0 0 0 0 0 0 0 0 0 0 0 0 ? ? bit mnemonic field name function [31:4] cced controlcurrented this pointer is advanc ed to the next ed after serving the present one. the hc continues processing the list from where it left off in the last frame. when it reaches the end of the control list, the hc checks the controllistfilled field of hccommands tatus. if set, the hc copies the content of hccontrolheaded to hccontrolcurrented and clears the bit. if it is not set, the hc does nothing. hcd is allowed to modify this register only when the controlliste nable field of hccontrol is cleared. when set, hcd only reads the instantaneous value of this register. initially, this is set to zero to indicate the end of the control list. [3:0] reserved a ddress = (0xf450_0000) + (0x0024)
tmpa901cm tmpa901cm- 790 2010-07-29 11. hcbulkheaded register the hcbulkheaded register contains the physical address of the first endpoint descriptor of the bulk list. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol bhed read/write (hcd) r/w read/write (hc) r reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 1110987654 3 2 10 bit symbol bhed reserved read/write (hcd) r/w read/write (hc) r reset state 0 0 0 0 0 0 0 0 0 0 0 0 ? ? bit mnemonic field name function [31:4] bhed bulkheaded the hc traverses the bulk list starting with the hcbulkheaded pointer. the content is loaded from hcca during the initialization of the hc. [3:0] reserved a ddress = (0xf450_0000) + (0x0028)
tmpa901cm tmpa901cm- 791 2010-07-29 12. hcbulkcurrented register the hcbulkcurrented register contains the physical address of the current endpoint of the bulk list. as the bulk list will be served in a round-robin fashion, the endpoints will be ordered according to their order of insertion to the list. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol bced read/write (hcd) r/w read/write (hc) r/w reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 1110987654 3 2 10 bit symbol bced reserved read/write (hcd) r/w read/write (hc) r/w reset state 0 0 0 0 0 0 0 0 0 0 0 0 ? ? bit mnemonic field name function [31:4] bced bulkcurrented this is advanced to the next ed after the hc has served the present one. the hc continues processing the list from where it left off in the last frame. when it reaches the e nd of the bulk list, the hc checks the bulklistfilled field of hccommand status. if set, the hc copies the content of hcbulkheaded to hcbulk currented and clears the bit. if it is not set, the hc does nothing. hcd is only allowed to modify this register when the bulklistenable fi eld of hccontrol is cleared. when set, hcd only reads the instantaneous val ue of this register. this is initially set to zero to indicate the end of the bulk list. [3:0] reserved a ddress = (0xf450_0000) + (0x002c)
tmpa901cm tmpa901cm- 792 2010-07-29 13. hcdonehead register the hcdonehead register contains the physical address of the last completed transfer descriptor that has been added to the done queue. in normal operation, the host controller driver should not need to read this register as its content is periodically written to the hcca. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol dh read/write (hcd) r read/write (hc) r/w reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 1110987654 3 2 10 bit symbol dh reserved read/write (hcd) r read/write (hc) r/w reset state 0 0 0 0 0 0 0 0 0 0 0 0 ? ? bit mnemonic field name function [31:4] dh donehead when a td is completed, the hc writes the content of hcdonehead to the nexttd field of the td. the hc then overwrites the content of hcdonehead with the address of this td. this is set to zero whenever the hc writes the content of this register to hcca. it also sets the writebackdonehead field of hcinterruptstatus. [3:0] reserved a ddress = (0xf450_0000) + (0x0030)
tmpa901cm tmpa901cm- 793 2010-07-29 14. hcfminterval register the hcfminterval register contains a 14-bit va lue which indicates the bit time interval in a frame, (i.e., between two consecutive so fs), and a 15-bit value indicating the full speed maximum packet size that the host controller may transmit or receive without causing scheduling overrun. the host contro ller driver may carry out minor adjustment on the frameinterval by writing a new value over the present one at each sof. this provides the programmability required for the host controller to synchronize with an external clocking resource and to adjust any unfixed local clock offset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol fit fsmps read/write (hcd) r/w r/w read/write (hc) r r reset state 0 tbd 15 14 13 12 1110987654 3 2 10 bit symbol reserved fi read/write (hcd) r/w read/write (hc) r reset state 1 0 1 1 1 0 1 1 0 1 1 1 1 1 ? ? bit mnemonic field name function [31] fit frameinterval toggle hcd toggles this bit each time it l oads a new value to frameinterval. [30:16] fsmps fslargestdata packet this field specifies a value whic h is loaded into the largest data packet counter at the beginning of each frame. the counter value represents the largest amount of dat a in bits which can be sent or received by the hc in a single trans action at any given time without causing a scheduling overrun. the field value is calculated by hcd. [15:14] reserved [13:0] fi frameinterval this field specifies t he interval between two consecutive sofs in bit times. the nominal value is set to be 11,999. hcd should store the current value of this field before resetting the hc. by setting the hostcontrollerreset field of hccommandstatus the hc resets this field to its nominal value. hcd may choose to restore the stored value upon the completion of the reset sequence. a ddress = (0xf450_0000) + (0x0034)
tmpa901cm tmpa901cm- 794 2010-07-29 15. hcfmremaining register the hcfmremaining register is a 14-bit down counter showing the bit time remaining in the current frame. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol frt reserved read/write (hcd) r read/write (hc) r/w reset state 0 15 14 13 12 1110987654 3 2 10 bit symbol reserved fr read/write (hcd) r read/write (hc) r/w reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? bit mnemonic field name function [31] frt frameremaining toggle this bit is loaded from the framei ntervaltoggle field of hcfminterval whenever frameremaining reaches 0. this bit is used by hcd for the synchronization between fminterval and fmremaining. [30:14] reserved [13:0] fr frameremaining this c ounter is decremented at each bit time. when it reaches zero, it is reset by loading the frameinterva l value specified in hcfminterval at the next bit time boundary. when entering the usboperational state, the hc re-loads the content with t he frameinterval of hcfminterval and uses the updated value from the next sof. a ddress = (0xf450_0000) + (0x0038)
tmpa901cm tmpa901cm- 795 2010-07-29 16. hcfmnumber register the hcfmnumber register is a 16-bit counter. it provides a timing reference among events happening in the host controller and the host controller driver. the host controller driver can use the 16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to the register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol reserved read/write (hcd) read/write (hc) reset state 15 14 13 12 1110987654 3 2 10 bit symbol fn read/write (hcd) r read/write (hc) r/w reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? bit mnemonic field name function [31:16] reserved [15:0] fn framenumber this is increment ed when hcfmremaining is re-loaded. it will be rolled over to 0x0000 after 0xffff. when entering the usboperational state, this will be incremented automatically. the content will be written to hcca after the hc increments the framenumber at each frame boundary and sends a sof but before the hc reads the first ed in that frame. after writing to hcca, the hc will set startofframe in hcinterruptstatus. a ddress = (0xf450_0000) + (0x003c)
tmpa901cm tmpa901cm- 796 2010-07-29 17. hcperiodicstart register the hcperiodicstart register has a 14-bit programmable value which determines the earliest time the hc should star t processing the periodic list. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol reserved read/write (hcd) read/write (hc) reset state 15 14 13 12 1110987654 3 2 10 bit symbol reserved ps read/write (hcd) r/w read/write (hc) r reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? bit mnemonic field name function [31:14] reserved [13:0] ps periodicstart after a hardware reset, th is field is cleared. this is then set by hcd during hc initialization. the value is calculated roughly as 10% off from hcfminterval. a typical value will be 0x3e67. when hcfmremaining reaches the value specified, processing of the periodic lists will have priority over control/bulk processing. the hc will therefore start processing the interrupt list after completing the current control or bulk transaction that is in progress. a ddress = (0xf450_0000) + (0x0040)
tmpa901cm tmpa901cm- 797 2010-07-29 18. hclsthreshold register the hclsthreshold register contains an 11-b it value used by the host controller to determine whether to commit to the transfer of a maximum of 8-byte ls packet before eof. neither the host controller nor the host controller driver are allowed to change this value. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol reserved read/write (hcd) read/write (hc) reset state 15 14 13 12 1110987654 3 2 10 bit symbol reserved lst read/write (hcd) r/w read/write (hc) r reset state 0 1 1 0 0 0 1 0 1 0 0 0 ? ? bit mnemonic field name function [31:12] reserved [11:0] lst lsthreshold this fi eld contains a value which is compared to the frameremaining field prior to initiating a low-s peed transaction. t he transaction is started only if frameremaining is larger than this field. the value is calculated by hcd with the consi deration of transmission and setup overhead. a ddress = (0xf450_0000) + (0x0044)
tmpa901cm tmpa901cm- 798 2010-07-29 19. hcrhdescriptora register the hcrhdescriptora register is one of the two registers describing the characteristics of the root hub. reset values are implementation-specific. the descriptor length (11), descriptor type (tbd), and hub controller curr ent (0) fields of the hub class descriptor are emulated by hcd. all other fields are located in the hcrhdescriptora and hcrhdescriptorb registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol potpgt reserved read/write (hcd) r/w read/write (hc) r reset state 0 0 0 0 0 0 1 0 15 14 13 12 1110987654 3 2 10 bit symbol reserved nocp ocpm dt nps psm ndp read/write (hcd) r/w r/w r r/w r/w r read/write (hc) r r r r r r reset state 0 0 0 0 0 0 0 0 0 0 0 0 1 ? bit mnemonic field name function [31:24] potpgt poweronto powergoodtime this byte specifies the duration hcd has to wait before it accesses a powered-on port of the root hub. it is implementation-specific. the unit of time is 2 ms. the durat ion is calculated as potpgt 2 ms. [23:13] reserved [12] nocp noovercurrent protection this bit describes how the overcurrent status for the root hub ports is reported. when this bit is clear ed, the overcurrentprotectionmode field specifies global or per-port reporting. 0: overcurrent status is reported collectively for all downstream ports 1: overcurrent protection not supported [11] ocpm overcurrent protectionmode this bit describes how the overcurrent status for the root hub ports is reported. at reset, this fields shoul d reflect the same mode as that of powerswitchingmode. this field is valid only if the noovercurrentprotecti on field is cleared. 0: overcurrent status is reported collectively for all downstream ports 1: overcurrent status is reported on a per-port basis [10] dt devicetype this bit specifies that the root hub is not a compound device. the root hub is not permitted to be a compound device. this field should always read/write = 0. [9] nps nopower switching these bits are used to specify wh ether power switching is supported or whether ports are always powered. it is implementation-specific. when this bit is cleared, the powe rswitchingmode specifies global or per-port switching. 0: ports are power switched 1: ports are always powered on when the hc is powered on [8] psm powerswitching mode this bit is used to specify how th e power switching of the root hub ports is controlled. it is implementation- specific. this field is only valid if the nopowerswitching field is cleared. 0: all ports are powered at the same time. 1: each port is powered individually. this mode allows port power to be controlled by either the global switching or per-port switching. if the portpowercontrolmask bit is set, the port responds only to port power commands (set/clearportpower). if the port mask is cleared, then the port is controlled only by the global power switch (set/clearglobalpower). [7:0] ndp number downstreamports these bits specify the number of downstream ports supported by the root hub. it is implementation-specific. this module has one port, so 0x01 is read. a ddress = (0xf450_0000) + (0x0048)
tmpa901cm tmpa901cm- 799 2010-07-29 20. hcrhdescriptorb register the hcrhdescriptorb register is one of the two resisters for describing the characteristics of the root hub. these fields are written during initialization to correspond with the system operation. reset values are implementation-specific. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol ppcm read/write (hcd) r/w read/write (hc) r reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 1110987654 3 2 10 bit symbol dr read/write (hcd) r/w read/write (hc) r reset state 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? bit mnemonic field name function [31:16] ppcm portpower controlmask each bit indicates if a port is affected by a global power control command when powerswitchingmode of hcrhdescriptora is set. when set, the port's power state is only affected by per-port power control (set/clearportpower). when cleared, the port is controlled by the global power switch (set/clearglobalpower). if the device is configured to global switching mode (powerswitchingmode=0), this field is not valid. bit0: reserved bit1: ganged-power mask on port#1 [15:0] dr device removable each bit indicates a port of the root hub. when cleared, the attached device is removable. when set, the attached device is not removable. bit0: reserved bit1: device attached to port#1 a ddress = (0xf450_0000) + (0x004c)
tmpa901cm tmpa901cm- 800 2010-07-29 21. hcrhstatus register the hcrhstatus register is divided into two fields. the lower word of a dword represents the hub status field and the upper word repres ents the hub status change field. reserved bits should always be 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol crwe reserved ocic lpsc read/write (hcd) w r/w r/w read/write (hc) r r/w r reset state 0 0 15 14 13 12 1110987654 3 2 10 bit symbol drwe reserved oci lps read/write (hcd) r/w r r/w read/write (hc) r r/w r reset state 0 0 0 ? a ddress = (0xf450_0000) + (0x0050)
tmpa901cm tmpa901cm- 801 2010-07-29 ? bit mnemonic field name function [31] crwe clearremote wakeupenable writing a 1 clears deviceremotewakeupenable. writing a 0 has no effect. [30:18] reserved [17] ocic overcurrent indicator change this bit is set by hardware when a change occurs in the oci field of this register. hcd clears this bit by writing a 1. writing a 0 has no effect. [16] lpsc localpower statuschange (read)localpowerstatuschange the root hub does not support the local power status feature, and therefore this bit is always read as 0. (write)setglobalpower in global power mode (powerswitchingmode = 0), this bit is set to 1 to turn on power to all ports (clear portpowerstatus). in per-port power mode, it sets portpowerstatus only on ports whose portpowercontrolmask bit is not set. writing a 0 has no effect. [15] drwe deviceremote wakeupenable (read)deviceremotewakeupenable this bit enables a connectstatu schange bit as a resume event, causing a usbsuspend to usbresum e state transition and setting the resumedetected interrupt. 0: connectstatuschange is not a remote wakeup event. 1: connectstatuschange is a remote wakeup event. (write) writing a 1 sets deviceremotewakeupenable. writing a 0 has no effect. [14:2] reserved [1] oci overcurrent indicator this bit reports current conditi ons when the global reporting is implemented. when set, an overcurrent condition exists. when cleared, all power operations are normal. if per-port overcurrent protection is to be implemented, this bit should always be set to 0. [0] lps localpower status (read)localpowerstatus the root hub does not support the local power status feature, and therefore this bit is always read as 0. (write)clearglobalpower in global power mode (powerswitchingmode = 0), this bit is set to 1 to turn off power to all ports (clear portpowerstatus). in per-port power mode, this bit clears portpowerstatus of ports whose portpowercontrolmask bit is not set. writing a 0 has no effect.
tmpa901cm tmpa901cm- 802 2010-07-29 22. hcrhportstatus register the hcrhportstatus register is used to control and report port events on a per-port basis. numberdownstreamports of the hcrhdescriptora register represents the number of hcrhportstatus registers that are implemented in hardware. the lower word is used to reflect the port status, whereas the upper word reflects the status change bits. some status bits are implemented with special write behavior (see below). if a transaction (token through handshake) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes. reserved bits should always be written 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol reserved prsc ocic pssc pesc csc read/write (hcd) r/w r/w r/w r/w r/w read/write (hc) r/w r/w r/w r/w r/w reset state 0 0 0 0 0 15 14 13 12 1110987654 3 2 10 bit symbol reserved lsda pps reserved prs poci pss pes ccs read/write (hcd) r/w r/w r/w r/w r/w r/w r/w read/write (hc) r/w r/w r/w r/w r/w r/w r/w reset state x 0 0 0 0 0 0 ? ? ? bit mnemonic field name function [31:21] reserved [20] prsc portresetstatus change this bit is set at the end of the 10-ms port reset signal. hcd writes a 1 to clear this bit. writing a 0 has no effect. 0: port reset is not complete 1: port reset is complete [19] ocic portovercurrent indicatorchange this bit is valid only if overcurrent conditions are reported on a per-port basis. this bit is set when root hub changes the portovercurrentindicator bit. hcd writes a 1 to clear this bit. writing a 0 has no effect. 0: no change in portovercurrentindicator 1: portovercurrentindicator is changed [18] pssc portsuspend statuschange this bit is set when the full resume sequence is completed. this sequence includes the 20-s resume pulse, ls eop, and 3-ms resynchronization delay. hcd writes a 1 to clear this bit. writing a 0 has no effect. this bit is also cleared when resetstatuschange is set. 0: resume is not completed 1: resume is completed a ddress = (0xf450_0000) + (0x0054)
tmpa901cm tmpa901cm- 803 2010-07-29 ? bit mnemonic field name function [17] pesc portenable statuschange this bit is set when hardware events cause the portenablestatus bit to be cleared. changes from hcd writes do not set this bit. hcd writes a 1 to clear this bit. writing a 0 has no effect. 0: no change in portenablestatus 1: portenablestatus is changed [16] csc connectstatus change this bit is set whenever a connec t or disconnect event occurs. hcd writes a 1 to clear this bit. writing a 0 has no effect. if currentconnectstatus is cleared when a setportreset, setportenable, or setportsuspend write occurs, this bit is set to force the driver to re-evaluate the c onnection status since these writes should not occur if the port is disconnected. 0: no change in currentconnectstatus 1: currentconnectstatus is changed note: if the deviceremovable[ndp] bit is set, this bit is set only after a root hub reset to inform the system that the device is attached. [15:10] reserved [9] lsda lowspeed deviceattached (read)lowspeeddeviceattached this bit indicates the speed of the device attached to this port. when set, a low-speed device is attached to this port. when cleared, a full-speed device is attached to this port. this field is valid only when the currentconnectstatus is set. 0: a full-speed device is attached 1: a low-speed device is attached (write)clearportpower hcd clears the portpowerstatus bit by writing a 1 to this bit. writing a 0 has no effect.
tmpa901cm tmpa901cm- 804 2010-07-29 ? bit mnemonic field name function [8] pps portpower status (read)portpowerstatus this bit reflects the port?s power st atus, regardless of the type of power switching implemented. this bit is cleared if an overcurrent condition is detected. hcd sets this bit by writing setportpower or setglobalpower. hcd clears this bit by writing clearportpower or clearglobalpower. which power contro l switches are to be enabled is determined by powerswitchingmode and portpowercontrolmask[ndp]. in global switching mode (powerswitchingmode = 0), only set/clearglobalpower controls this bit. in per-port power switching (powerswitchingmode = 1), if the portpowercontrolmask[ndp] bit for the port is set, only set/clearportpower commands are enabled. if the mask is not set, only set/clearglobalpower commands are enabled. when port power is disabled, currentconnects tatus, portenablestatus, portsuspendstatus, and portresetstatus should be reset. 0: port power off 1: port power on (write)setportpower hcd writes a 1 to set the portpowerstatus bit. writing a 0 has no effect. note: this bit always reads 1 if power switching is not supported. [7:5] reserved [4] prs portreset status (read)portresetstatus when this bit is reset by a write to setportreset, port reset signaling is asserted. after reset is complete, this bit is cleared when portresetstatuschange is set. this bit cannot be set if currentconnectstatus is cleared. 0: port reset signal is not active 1: port reset signal is active (write)setportreset hcd sets the port reset signaling by writing a 1 to this bit. writing a 0 has no effect. if currentconnectstatus is cleared, this write does not set portresetstatus, but instead sets currentconnectstatuschange. this informs the driver that it attempted to reset a disconnected port.
tmpa901cm tmpa901cm- 805 2010-07-29 ? bit mnemonic field name function [3] poci portovercurrent indicator (read)portovercurrentindicator this bit is only valid when the root hub is configured in such a way that overcurrent conditions are reported on a per-port basis. if the per-port overcurrent reporting is not supported, this bit is cleared to 0. if cleared, all power operations are normal for this port. if set, an overcurrent condition exists on this port. this bit always reflects the overcurrent input signal. 0: no overcurrent condition 1: an overcurrent condition detected (write)clearsuspendstatus hcd writes a 1 to initiate a resume. writing a 0 has no effect. a resume is initiated only if portsuspendstatus is set. [2] pss portsuspend status (read)portsuspendstatus this bit indicates that the port is suspended or in the resume sequence. it is set by a setsuspendstate write and cleared when portsuspendstatuschange is set at the end of the resume interval. this bit is cleared when currentconnects tatus is set. this bit is also cleared when portresetstatuschange is set at the end of the port reset or when the hc is placed in the usbresume state. 0: port is not suspended 1: port is suspended (write)setportsuspend hcd sets the portsuspendstatus bit by writing a 1 to this bit. writing a 0 has no effect. if currentconnectstatus is cleared, this write does not set portsuspendstatus; instead it sets connectstatuschange. this informs the driver that it attempted to suspend a disconnected port.
tmpa901cm tmpa901cm- 806 2010-07-29 ? bit mnemonic field name function [1] pes portenable status (read)portenablestatus this bit indicates whether the por t is enabled or disabled. the root hub may clear this bit when an ov ercurrent condition, disconnect event, switched-off power, or opera tional bus error such as babble is detected. this change also caus es portenabledstatuschange to be set. hcd sets this bit by writing setportenable and clears it by writing clearportenable. this bit cannot be set when currentconnectstatus is cleared. this bit is also set, at the completion of a port reset when resetstatuschange is set or when port is suspend when suspendstatuschange is set. 0: port is disabled 1: port is enabled (write)setportenable hcd sets portenablestatus by writing a 1. writing a 0 has no effect. if currentconnectstatus is cleared, this write does not set portenablestatus, but instead sets connectstatuschange. this informs the driver that it attempted to enable a disconnected port. [0] ccs currentconnect status (read)currentconnectstatus this bit reflects the current state of the downstream port. 0: no device is connected 1: a device is connected (write)clearportenable hcd writes a 1 to this bit to clear the portenablestatus bit. writing a 0 has no effect. the currentconnectstatus is not affected by any write. note: this bit always reads 1 when t he attached device is nonremovable (deviceremoveable[ndp]).
tmpa901cm tmpa901cm- 807 2010-07-29 23. hcbcr0 register the hcbcr0 register controls clock supply fr om the usb bridge logic to the usb host core and the suspend state of the usb transc eiver. to enter power cut mode with the usb transceiver in the suspend state, write a 1 to the trans_susp bit. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit symbol res erve d trns susp ovc e reserved read/write r r/w r/w r reset state 0 1 0 0 15 14 13 12 1110987654 3 2 10 bit symbol reserved res erve d res erve d read/write r r/w r/w reset state 0 0 0 ? ? ?t? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? note: when the over current input enable bit is not set, the usbocn pin must be used as output port. ? bit mnemonic field name function [31] ? reserved [30] trns_susp transceiver suspend this bit controls the suspend state of the usb transceiver. to enter stop mode or power cut mode with the usb transceiver in the suspend state, set this bit to 1. 0: - (controlled by the usb host controller) 1: suspend [29] ovce usb host over current input enable usb host over current input enable 0y0: enable 0y1: disable [28:2] ? reserved [1:0] ? reserved write as zero a ddress = (0xf450_0000) + (0x0080)
tmpa901cm tmpa901cm- 808 2010-07-29 3.25.7 notes on setting 3.25.7.1 notes on usb clock setting before access the usb host circui ts(registe rs), please set the clkcr5= 0y1, and the usb host clock output is enable status. to use x1usb as the usb clock, set the procedure as following and can select the frequency at 1/4f pll or 1/3f pll . (1) when x1usb is used. ???????? syscr8 ?? 0yxxxx_x001 ; usbh_clksel=0y001 ; x1usb clock ???????? clkcr5 ? 0yxxx1_xxxx ; usbh_clken=1 ; usb host clock enable note 1: the setting for selecting x1usb should be made while the x1usb are in a stable state. note 2: before entering power cut mode (pmc), set clkcr5 = 0y0. after exiting power cut mode, make sure that x1usb is in a stable stat e before selecting x1usb as the usb clock. note 3: when stopping the usb, set clkcr5 = 0y0. (2) when f pll /4 is used after reset release (using the pll). in case of using x1=24mhz and 8pll ???????? syscr8 ?? 0yxxxx_x100 ; usbh_clksel=0y100 ; 1/4f pll of pll output clock ???????? clkcr5 ? 0yxxx1_xxxx ; usbh_clken=1 ; usb host clock enable note: the setting for selecting f pll hould be made while the pll clock is in a stable state. (3) when f pll /3 is used after reset release (using the pll). in case of using x1=24mhz and 6pll ???????? syscr8 ?? 0yxxxx_x010 ; usbh_clksel=0y010 ; 1/3f pll of pll output clock ???????? clkcr5 ? 0yxxx1_xxxx ; usbh_clken=1 ; clock enable for usb host note: the setting for selecting f pll hould be made while the pll clock is in a stable state. 3.25.7.2 notes on oscillator when using this de vice with a built-in usb host controller, it is recommended to use a crystal oscillator under 24mhz 100ppm based on the usb specification. to generate usb clocks by the built-in pll, the specifications provided by usb may not be satisfied depending on the implementation environment, condition, or fluctuation. to be certified for the usb logo complian ce, the 48mhz clock with an accuracy of 100ppm or lower must be input through x1usb. 3.25.7.3 notes on entering power cut mode to shift to the p ower cut mode, set the usb to suspend state first. after state in power cut mode, the power supply of usb host controller which are dvcc1a and avcc3h can be turn off by external circuits.
tmpa901cm tmpa901cm- 809 2010-07-29 3.25.8 restrictions on the usb host controller 1. for an isochronous transfer, a frame number to be transferred is defined in an isochronous transfer descriptor (itd). however, when frame numbers are not synchronized between the host and software, and if the descriptor to be executed with a previous frame is scheduled later, the host determines that a time error has occurred and writes back dataoverrun to the cc field of the itd. however, if the following conditions are met, the host will write back inappr opriate status (noerror). the above problem occurs if both the following two conditions are met: 1. itd.fc[2:0] = r[2:0] 2. itd.fc[2:0] < r[15:0] where itd.fc indicates the number of times an itd is executed, and r = hcfmnumber (current frame number) ? itd.sf (transfer start frame number). make sure that each itd is synchronized to the current frame number. if not, this itd should not be linked. 2. for a low-speed in transfer by the host, the usb 2.0 specification defines the inter-packet delay (the time from when the host receives a data packet to when the host transfers a handshake packet) as less than 7.5 bit times. in this product, however, the inter-packet delay is about 9.2 bit times in the worst case. 3. if a fatal error occurs on the usb system and the host detects this error (e.g., master abort, target abort, etc. on the pci bus), the ohci core sets the unrecoverableerror (ue) bit in the hcinterruptstatus register. at this time, if the unrecoverable error (ue) bit is set and the ue bit in the hcinterruptenable register is set, a hardware interrupt is generated. after this interrupt is detected, a software reset (hccommandstatus.hcr = 1?b1) is required to recover from the ue state, and the host then moves to the suspend state. after the software reset, ohci registers are initialized. if a remote wake-up occurs on the device, the host remains in the suspend state. when the remote wake-up function is to be used, a program for recovering from the suspend state must be implemented. programming examples: 1) after initializing ohci registers by a software reset, set a value other than usbsuspend (2?b11) to the hccontrol.hcfs field. 2) when a remote wake-up is detected, th e hcinterruptstatus.rd bit is set to 1?b1. after detecting this interrupt, set a value other than usbsuspend (2?b11) to the hccontrol.hcfs field. 4. when hcrhdescriptora.nps[9] is set to 1?b1 when an overcurrent is occurred, portresetstatus.prs[4] and portsuspendstatus. pss[2] of the hcrhportstatus register is not cleared. therefore, do not set hcrhdescriptora.nps[9] = 1'b1 and hcrhdescriptorb.dr[portno] = 1?b1.
tmpa901cm tmpa901cm- 810 2010-07-29 5. to set the hcrhstatus.drwe[15] when co nnecting with full-speed/low-speed device, the status is not shifted from usbsuspend to usbresume even remote wake-up is occurred. as some restrictions, the status is not shifted from usbsuspend to usbresume even if using remote wake-up event. however, hcinterruptstatus.rd[3] is set appropriately at the same time, so that software can be modified to switch the status by checking this bit. when not to use remote wake-up even t, do not set the hcrhstatus.drwe[15] to 1?b1. 6. when supporting the overcurrent for device system, noovercurrentprotection.nocp[12] of hcrhdescriptora register must set to 1'b0. 7. to not use the overcurrent detection function of the usb host controller, the pt5 (usboc) pin must be used as an output port or a fixed output. 8. when isochronous transfers are used, do not generate schedule overrun. 9. if port is disabled afte r port reset is performed, perform reset port again.
tmpa901cm tmpa901cm- 811 2010-07-29 3.25.9 connection example bus power switch device: tps2052 from texas instruments mic2526-1bm from micrel mic2536-1bn from micrel transient voltage suppressor device: sn75240 from texas instruments resistance precision: 5% resistance rating: 1/2 w for 27 ohms (recommended) capacitor: low esr type 120 uf capacitor (os-con, etc.) (recommended) note 1: do not apply voltages exceeding the absolute maximum rating. note 2: when designing your board, make sure that t he hdp and hdm- pins are placed at the equal distance from the usb a receptacle. note 3: a suppressor device is not required in the usb specifications. note 4: after releasing a reset, usbocn and usbpon pin will be input mode. these pins need to correspond in the circuit. mcu hdp hdm usbocn usbpon (note 1) (note 1) transient voltage suppressor * active-low signal power switch micrel 3.3v 100k
tmpa901cm tmpa901cm - 812 2010-07-29 3.26 ofd (oscillation frequency detector) 3.26.1 outline the oscillation frequency detector (ofd) generates a reset when the high-frequency oscillation frequency (f osch ) falls or rises outside of the normal frequency range specified by the lower and higher detection frequency setting registers. when an abnormal frequency condition is detected, it can be notified to an internal reset circuit. the high-frequency clock (f osch ) is used as a detection clock, and the low-frequency clock (f s : 32 khz) is used as a reference clock of the ofd. if the 32 khz reference clock stops due to an external cause, etc., the ofd detects an abnormal condition and resets the internal circuitry. note: in the pcm mode, the ofd circuitry is not powe red and is not operational. so stop the ofd operation before the pcm execution. ???????
tmpa901cm tmpa901cm - 813 2010-07-29 ? 3.26.2 ofd block diagram ? ??
tmpa901cm tmpa901cm - 814 2010-07-29 ? 3.26.3 description of operation 1) reset generation and release the ofd generates a reset on the second or third rising edge of the low-frequency clock after detecting a clock (f osch ) fault (including a stop state). the ofd is also capable of detecting low-frequency clock faults. when a high-frequency clock fault occurs and the frequency ratio goes outside the range specified in the clksmn and clksmx register s, the ofd generates a reset on the second rising edge of the low-frequency clock after dete cting a clock fault. generation of a reset does not clear the clock fault detection, and the re set is released when the clock resumes stable oscillation and the frequency ratio returns to the specified normal range. in the case of the low-frequency clock, a reset is generated when the clock stops. the reset is not released until the low-frequency clock resu mes oscillation. when both fs and fosch clock are in unstable, the operation is not guaranteed. figure 3.26.1 timing of reset generating (fosch clock fault) figure 3.26.2 timing of reset releasing (fosch clock fault) fosch clock fault resume fosch clock ofd_reset ofd_reset
tmpa901cm tmpa901cm - 815 2010-07-29 figure 3.26.3 timing of reset gene rating and releasing (fs clock fault) note : a clock fault detection reset is also generated if either of the high-frequency or low-frequency clock frequency temporarily goes outside the specified range of the frequency ratio due to noise, etc. 2) initialization of ofd registers the ofd registers (clkscr1, clkscr2, clkscr3, clksmn and clksmx) are initialized by an external reset (resetn pin = low). the ofd registers are also initialized when the pcm mode is exited. note: the ofd registers are not initialized by a wdt reset or ofd reset. 3) how to confirm the clock fault detection the fault detection can be confirmed by of d status flag (clkscr3=1) in ofd circuit. reset signal will be asserted after fs clock is stopped 51 3cyclesormoreatfosch div4 reset signal will be resumed after on the fifth edge of fs clock ofd_reset fs 1/4 fosch
tmpa901cm tmpa901cm - 816 2010-07-29 4) how to set the minimum and maximum clock fault detection values the configuration frequency = (frequency) + (frequency error ratio) + (ofd circuit error ratio) + the actual registers (clksmn and clksmx) setting value is calculated by above the configuration values the following shows the calculation formulas and register setting examples when f osch = 24 mhz (assuming the guaranteed oscillation frequency error is 1%). ? example of calculation for the configuration frequency the ofd of this product is capable of detecting f osch deviations exceeding 10%. it is therefore recommended to set clksmn and clksmx to approximately 10% of f osch . frequency (low) = 24 mhz*(1-10%) = 21.6 mhz frequency (high) = 24 mhz*(1+10%) = 26.4 mhz ? how to set the clksmn and clksmx registers frequency (low) = 21.6 mhz frequency (high) = 26.4 mhz when the oscillation clock frequency goes outside the specified range, an ofd reset is generated. clksmn set value = 50165 410 32.768 21.6 4 fs )( -3 xa low frequency = =  (fractions to be rounded up) clksmx set value = 90201 410 32.768 26.4 4 fs )( 3- xc high frequency = =  (fractions to be rounded up) ? ? ? ) ? ???k?{{k????k??k k??`y??? ?
tmpa901cm tmpa901cm - 817 2010-07-29 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? target detection frequencies: how to calc ulate the subharmonic and harmonic of f osch (assuming the guaranteed oscillation frequency error is 1%) sub-harmonic (allowing for the maximum high-frequency oscillator error) = 24 mhz (1+0.01) 2 = 12.12 mhz ? harmonic (allowing for the minimum high-frequency oscillation error) = 24 mhz (1-0.01) 2 = 47.52 mhz the following shows the recommended configuration when f osch = 24 mhz and 10mhz (assuming the oscillation frequency error and the ofd capable of detecting are 10% totally). ??

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tmpa901cm tmpa901cm - 818 2010-07-29 ? 3.26.4 register list ? ? register name address (base+) description clkscr1 0x0000 oscillation frequency detection control register 1 clkscr2 0x0004 oscillation frequency detection control register 2 clrscr3 0x0008 oscillation frequency detection control register 3 clksmn 0x0010 lower detection frequency setting register clksmx 0x0020 higher detection frequency setting register ? base address = 0xf009_0000
tmpa901cm tmpa901cm - 819 2010-07-29 ? 1. clkscr1 (oscillation frequency detection control register 1) ? ???? bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7:0] clkwen r/w 0x06 ofd register write enable code: 0x06: disable writing to clkscr2, clkscr3, clksmn and clksmx 0xf9: enable writing to clkscr2, clkscr3, clksmn and clksmx others: reserved (note 1) ? ? [explanation] a. < clkwen > 0x06: disable writing to the clkscr2, clkscr3, clksmn and clksmx registers 0xf9: enable writing to the clkscr2, clkscr3, clksmn and clksmx registers note 1: only ? 0x06? and ? 0xf9 ? can be written to clkscr1. all values other than ?0xf9? are handled as ?0x06?, disabling writing to clkscr2, clkscr3, clksmn and clksmx. ? 2. clkscr2 (oscillation frequency detection control register 2) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7:0] clksen r/w 0x00 ofd operation enable code: 0x00: disable 0xe4: enable others: invalid (note 1) ? [explanation] a. < ofden > 0x00: enable the ofd operation 0xe4: disable the ofd operation note 1: only ?0x00? and ?0xe4? can be written to clkscr2. writing a value other than ?0x00? and ?0xe4? to clkscr2 is invalid (the register value cannot be changed.) note 2: when the disable code ?0x06? is written to clkscr1, writing to clkscr2 is disabled and any write attempts are ignored. even when write oper ation is disabled, clkscr2 can be read. note3: it takes 2 fs cycles in maximums until the configur ation is executed after writing into register. so when writing it in this register once, other configur ations should be set after passing 2 fs cycles. the enable/disable status flag is not available. the read data value and the operating state are not much in time-lag period. ? a ddress = (0xf009_0000)+(0x0000) a ddress = (0xf009_0000)+(0x0004)
tmpa901cm tmpa901cm - 820 2010-07-29 ? 3. clkscr3 (oscillation frequency detection control register 3) bit bit symbol type reset value description [31:2] ? ? undefined read as undefined. write as zero. [1] resen r/w 0y0 ofd reset enable: 0y0: disable 0y1: enable [0] clksf r/w 0y0 high speed oscillation frequency detection flag: read: 0y0: osc normal 0y1: osc abnormal write: 0y0: invalid 0y1: clear the flag to ?0? ? [explanation] a. 0y0: disable ofd reset. 0y1: enable ofd reset. when an abnormal co ndition is detected, an internal reset is generated. note: this resen bit takes 2 fs cycles in maximums until the configuration is executed after writing into this bit. this bit can be poling whether or not the configulation is set and after that the other register setting can be done. b. read 0y0: the frequency of the high-frequency oscillation clock is within the specified range. 0y1: the frequency of the high-frequency oscillation clock is outside the specified range. =0y1 remains set until it is cleared. even when the high-frequency oscillation clock frequency returns to the specified range. ? . write 0y0: invalid 0y1: clear the flag to ?0? a ddress = (0xf009_0000)+(0x0008)
tmpa901cm tmpa901cm - 821 2010-07-29 ? 4. clksmn (lower detection frequency setting register) bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7:0] ldfs r/w 0xa5 low detection frequency setting : ? 5. clksmx (higher detection frequency setting register) ? ???? bit bit symbol type reset value description [31:8] ? ? undefined read as undefined. write as zero. [7:0] hdfs r/w 0xc9 high detection frequency setting : ? ? [explanation] and < hdfs > these registers are for detection frequency setting value. note 1: clksmn and clksmx cannot be written while the frequency detection operation is enabled (clkscr2 = ?0xe4?) or writing to the ofd registers is disabled (clkscr1="0x06"). note 2: clksmn and clksmx are protected from writ e operation by writing ?0x06? to clkscr1. these registers can be read regardless of the setting of clkscr1. note 3: the values to be set to clksmn and clksmx should be determined depending on the clock frequencies to be used to satisfy the condition clksm n < clksmx. for how to calculate the clksmn and clksmx set values, see examples in 3.26.3 ?description of operation?. note 4: the setting of clksmn and clksmx should be set with enough safe including several percent error. otherwise the internal reset might be always assert into the cpu. (deadlock state) a ddress = (0xf009_0000)+(0x0010) a ddress = (0xf009_0000)+(0x0020)
tmpa901cm tmpa901cm - 822 2010-07-29 3.26.5 programming example ?
tmpa901cm tmpa901cm - 823 2010-07-29 1) programming example of ofd operation enable/disable -- enable setting example -- clkscr1=0xf9 ; ofd register write enable ????? clkscr2=0x00 ; ofd circuits operation disable ????? wait fs 2cycles ?? clkscr3=0x03 ; resen enable clear osc flag ????? poling until the resen=1 state ; check the resen bit status ????? set the clksmn and the clksmx registers ????? clkscr2=0xe4 ; ofd circuits operation enable ??? wait fs 2cycles ????? clkscr1=0x06 ; ofd register write disable -- disable setting example -- clkscr1=0xf9 ; ofd register write enable ????? clkscr2=0x00 ; ofd circuits operation disable ????? wait fs 2cycles ??? clkscr3=0x01 ; resen disable ????? poling until the resen=0 state ; check the resen bit status ????? clkscr1=0x06 ; ofd register write disable note: in the pcm mode, the ofd circuitry is not powe red and is not operational. so stop the ofd operation before the pcm execution.
tmpa901cm tmpa901cm- 824 2010-07-29 4. electrical characteristics 4.1 absolute maximum ratings symbol parameter rating unit dvcc3io dvccm -0.3 to 3.8 dvcc1a dvcc1b dvcc1c -0.3 to 2.0 avcc3ad avdd3t avdd3c avcc3h power supply voltage -0.3 to 3.8 v v in input voltage -0.3 to dvcc3io + 0.3 (note 1) -0.3 to dvccm + 0.3 (note 2) -0.3 to avcc3ad + 0.3 (note 3) -0.3 to avdd3t + 0.3 (note 4) -0.3 to avdd3c + 0.3 (note 4) -0.3 to avcc3h + 0.3 v i ol output current (per pin) 5 ma i oh output current (per pin) -5 ma  iol output current (total) 80 ma  ioh output current (total) -80 ma p d power consumption (ta = 85o c) 800 mw t solder soldering temperature (10s) 260 c t stg storage temperature -65 to 150 c t opr operating temperature -20 to 85 c note 1: do not exceed the absolute maximum rating of dvcc3io (sm2-4, sm6,sm7, sn0-2, sp0-5, pa0-3, pb0-3, pc2-4, pc6-7, pn0, pn1, pt0-7, pu0-7, pv0-7) note 2: do not exceed the absolute maximum rating of dvccm ? (sa0-7, sb0-7, se0-7, sf0-7, sg0-7, sh2,sh3,sh4,sh7, sj0-6, sk0, sk1, sk4, sk5, sl0-2, sl4-sl6) note 3: for pd4-7, vrefh, vrefl the absolute maximum rating of avcc3ad is applied. note 4: for the usb, ddm and ddp- pins, the abs olute maximum rating of avcc3t/3c is applied. note 5: the absolute maximum ratings are rated values that must not be exceeded during operation, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rati ng is exceeded, the device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when desigining produc ts that include this device, ensur e that no absolute maximum rating value will ever be exceeded. solderability te s t parameter test condition note use of sn-37pb solder bath solder bath temperature = 230 c, dipping time = 5 seconds the number of times = one, use of r-type flux solderability use of sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c, dipping time = 5 seconds the number of times = one, use of r-type flux pass: solderability rate until forming 95%
tmpa901cm tmpa901cm- 825 2010-07-29 4.2 dc electrical characteristics operating voltage symbol parameter min typ max unit condition dvcc3io general i/o power supply voltage (dvcc3io) (dvsscomx = avss = 0v) 3.0 3.3 3.6 dvccm_1 memory i/o power 3.0 3.3 3.6 dvccm_2 memory i/o power 1.7 1.8 1.9 avcc3ad adc power 3.0 3.3 3.6 avdd3t/3c usb device power 3.15 3.3 3.45 avcc3h usb host power 3.0 3.3 3.6 dvcc1a internal power a dvcc1b internal power b dvcc1c high clk oscillator and pll power 1.4 1.5 1.6 v x1 = 10 to 27mhz cpu clk (to 200mhz) xt1 = 30 to 34khz it is assumed that all power supply pins of the same rail are electrically connect ed externally and are supplied with the equal voltage. note: the power of i2s function is supplied by dvcc3io.
tmpa901cm tmpa901cm- 826 2010-07-29 input voltage (1) symbol parameter min typ max unit condition vil0 input low voltage for sm2, sm6-7, sn0-2, sp0-3 pa0-3, pt0-7 ? 0.3 dvcc3io 3.0 dvcc3io 3.6v vil1 ? 0.3 dvccm 3.0 dvccm 3.6v seldvccm = 1 vil2 input low voltage for sa0-7, sb0-7, sl4-6 ? 0.3 dvccm 1.7 dvccm 1.9v seldvccm = 0 vil5(note) input low voltage for pd4-7 ? 0.3 avcc3ad 3.0 avcc3ad 3.6v vil6 input low voltage for sm4, pc6, pc7, pn0, pn1 -0.3 ? 0.25 dvcc3io v 3.0 dvcc3io 3.6v note: when ports pd4 to pd7 are used as general-purpose inputs. input voltage (2) symbol parameter min typ max unit condition vih0 input high voltage for sm2, sm6-7, sn0-2, sp0-3 pa0-3, pt0-7 0.7 dvcc3io ? dvcc3io + 0.3 3.0 dvcc3io 3.6 vih1 0.7 dvccm ? dvccm + 0.3 3.0 dvccm 3.6 vih2 input high voltage for sa0-7, sb0-7, sl4-6 0.7 dvccm ? dvccm + 0.3 1.7 dvccm 1.9 vih5 (note) input high voltage for pd4-7 0.7 adcc3ad ? avcc3ad + 0.3 3.0 avcc3ad 3.6 vih6 input high voltage for sm4, pc6, pc7, pn0, pn1 0.75 dvcc3io ? dvcc3io + 0.3 v 3.0 dvcc3io 3.6v note: when ports pd4 to pd7 are used as general-purpose inputs.
tmpa901cm tmpa901cm- 827 2010-07-29 output voltage (1) symbol parameter min typ max unit condition vol0 output low voltage for sm3, sp4, sp5, pb0-3, pc2-4, pc6, pc7, pn0, pn1, pt0-7 iol = 2.0 ma 3.0 dvcc3io 3.6v vol1 iol = 2.0 ma 3.0 dvccm 3.6v vol2 output low voltage for sa0-7, sb0-7, se0-7, sf0-7, sg0-7, sh2-4, sh7, sj0-6, sk0-1, sk4-5, sl0-2, sl4-5 iol = 2.0 ma 1.8 dvccm 1.9v vol5 output low voltage for pd4-7 ? ? 0.4 v iol = 2.0 ma 3.0 avcc3ad 3.6v output voltage (2) symbol parameter min typ max unit condition voh0 output high voltage for sm3, sp4, sp5, pb0-3, pc2-4, pc6, pc7, pn0, pn1, pt0-7 dvcc3io 0.4 ioh = -1.0 ma 3.0 dvcc3io 3.6v voh1 dvccm 0.4 ioh = -1.0 ma 3.0 dvccm 3.6v voh2 output high voltage for sa0-7, sb0-7, se0-7, sf0-7, sg0-7, sh2-4, sh7, sj0-6, sk0-1, sk4-5, sl0-2, sl4-5 dvccm 0.4 ioh = -1.0 ma 1.8 dvccm 1.9v voh5 output high voltage for pd4-7 avcc3ad 0.4 ? ? v ioh = -1.0 ma 3.0 avcc3ad 3.6v
tmpa901cm tmpa901cm- 828 2010-07-29 others symbol parameter min typ max unit condition imon internal resistor (on) mx, my pins ? ? 30 vol = 0.2v imon internal resistor (on) px, py pins ? ? 30 voh = avcc3ad ? 0.2v 3.0 ? avcc3ad ? 3.6v ili input leakage current ? 0.02 5 a ilo output leakage current ? 0.05 10 a r pull up/down resistor for resetn, pa0-3, pd6 30 50 70 k cio pin capacitance ? 1.0 ? pf fc = 1mhz vth schmitt width for sm4, pa0-3, pd6, pd7, pc6, pc7, pn0-1, pt4-6 ? 0.6 ? v 3.0 ? dvcc3io ? 3.6v note 1: typical values show those with ta = 25 c and dvcc3io = 3.3 v, dvccm = 3.3v or dvccm = 1.8v dvcc1a,1b,1c = 1.5v unless otherwise noted. note 2: the above values do not apply when debug mode is used.
tmpa901cm tmpa901cm- 829 2010-07-29 symbol parameter min typ max unit condition ? 1.8 3.0 dvcc3io = 3.6v ? 10 12 dvcc3lcd = 3.6v ? 5 7 avcc3ad = 3.6v ? 50 ? avdd3t = 3.3v avdd3c = 3.3v ? 0.7 2.0 avcc3h = 3.3v 28 36 only sdram access ? 13 17 dvccm = 3.6v only norf access 15 19 only sdram access ? 7 9 dvccm = 1.9v only norf access ? 136 206 pll_on f fclk = 200mhz ta 70 c dvcc1a = 1.6v dvcc1b = 1.6v dvcc1c = 1.6v normal (note2) 105 205 ma pll_on f fclk = 150mhz ta 85 c dvcc1a = 1.6v dvcc1b = 1.6v dvcc1c = 1.6v ? 6.1 10 dvcc3io = 3.6v dvccm = 3.6v dvcc3lcd = 3.6v avcc3ad = 3.6v avdd3t = 3.6v avdd3c = 3.6v avcc3h = 3.6v icc cpu halt 16 116 ma pll_off f fclk = 25mhz dvcc1a = 1.6v dvcc1b = 1.6v dvcc1c = 1.6v operationg conditions: normal cpu: drystone rev2.1 instruction cache : on, data cache: on program execution area : internal ram, data area: internal ram, stack area: internal ram usb: default condition lcdc: hvga_16bpp a/dc: 5 s repeat conversion i 2 s, cms: stop sdhc: stop uart: 480kbps transmission ssp: 100kbps transmission pwm: 100khz output sdram: 100mhz cl=2 bl=8 32bit bus read/write (external bus start operation duty is approximately 17 % ) or norf: asynchronous norf 160 ns access 16bit bus continuous read cpu halt cpu: halt, peripheral circ uit: tsb original program usb: suspend lcdc: simplicity operation (vram: internal ram) a/dc, i 2 s, cms, uart, ssp, pwm, external memory access: no operarion note 1: typical values show those with ta = 25c, dvcc3io = avcc3h = 3.3v, dvccm = 3.3v or dvccm = 1.8v, dvcc1a,1b,1c = 1.5v unless otherwise noted. note 2: ic measurement conditions: cl = 25 pf for bus pins, other output pins = open, input pins = level fixed note 3: the above values do not apply when debug mode is used.
tmpa901cm tmpa901cm- 830 2010-07-29 symbol parameter min typ max unit condition 100 ta 85 c 25 ta 70 c 4.5 15 ta 50 c dvcc3io = 3.6v dvccm = 3.6v avcc3ad = 3.6v avdd3t = open avdd3c = open avcc3h = open 230 ta 85 c 135 ta 70 c icc power cut mode (with pmc function) ? 1.5 70 a ta 50 c dvcc1a = 0v dvcc1b = 1.6v, dvcc1c = 0v xt = 32khz x1,x2 = off note 1: typical values show those with ta = 25c, dvcc3io = 3.3 v, dvccm = 3.3v or dvccm = 1.8v, dvcc1a,1b,1c = 1.5v, unless otherwise noted. note 2: ic measurement conditions: cl = 50 pf for bus pins, other output pins = open, input pins = level fixed (operating at 8-wait access for external memory) note 3: the above values do not apply when debug mode is used.
tmpa901cm tmpa901cm- 831 2010-07-29 4.3 ac electrical characteristics all ac specifications shown below are the measurement results under the following conditions unless specified otherwise. ac measurement conditions ? the letter ?t? used in the equations in the table represents the period of internal bus frequency (f hclk ) which is one-half of the cpu clock (f fclk ). ? output level: high = 0.7 dvccm, low = 0.3 dvccm ? input level: high = 0.9 dvccm, low = 0.1 dvccm note: the ?equation? column in the table show s the specifications under the conditions dvccm = 1.7 to 1.9 v or dvccm = 3.0 to 3.6 v and dvcc1a = dvcc1b = dvcc1c = 1.4 to 1.6 v. 4.3.1 basic bus cycles read cycle (asynchronous mode) equation no. parameter symbol min max 100 mhz n=10 m=3 k=10 l=6 96 mhz n=10 m=3 k=10 l=6 48 mhz n=5 m=1 k=5 l=3 unit 1 internal bus period ( = t) note) t cyc 10 800 10.0 10.4 20.8 2 a0-a23 valid to d0-d15 input t ad (n)t ? 15.0 85.0 89.2 89.2 3 smcoen fall to d0-d15 input t oed (n-m)t ? 10.0 60.0 62.8 73.3 4 smcoen low level pulse width t oew (n-m)t ? 8.0 62.0 64.9 75.3 5 a0-a23 valid to smcoen fall t aoe mt ? 5.0 25 26.3 15.8 6 smcoen rise to d0-d15 hold t hr 0 0 0 0 7 smcoen high level pulse width t oehw mt ? 8.0 22 23.3 12.8 ns write cycle (asynchronous mode) 8 d0-d15 valid to smcwen rise t dw (l+1)t ? 10.0 60.0 62.9 73.3 9 d0-d15 valid to smcwen rise (bls=1) t sds (l+1)t ? 10.0 60.0 62.9 73.3 10 smcwen low level width t ww lt ? 8.0 52.0 54.5 54 11 a0-a23 valid to smcwen fall t aw t ? 5.0 5.0 5.4 15.8 12 smcwen rise to a0-a23 hold t wa (k-l-1)t ? 5.0 25.0 26.3 15.8 13 smcwen rise to d0-d15 hold t wd (k-l-1)t ? 5.0 25.0 26.3 15.8 14 smcoen rise to d0-d15 output t oeo 2 2.0 2.0 2.0 15 data byte control to write complete time t sbw lt ? 8.0 52.0 54.5 54.5 ns ? the variables used in the equations in the table are defined as follows: n = number of t rc cycles m = number of t ceoe cycles k = number of t wc cycles l = number of t wp cycles measuring condition connection 1. dvcc3io 0.7 seldvccm dvcc3io software configuration 1. pmcdrv = 0y11 (full drive at 1.8 0.1v) 2. pmcdrv = 0y01 (half drive at 3.3 0.3v) loaded capacitance cl ( 25 pf note: the internal bus cycle is t=10ns minimum va lue when the guaranteed temperature is 0 to 70 degree. the internal bus cycle is t=13.3ns minimum value wh en the guaranteed temperature is -20 to 85 degree.
tmpa901cm tmpa901cm- 832 2010-07-29 (1) asynchronous memory read cycle (trc = 4, tceoe = 1) a0 to a23 smcben t cl t cyc t ch t ad t oew t oed t oehw t aoe data in p ut t hr smccsn smcoen smcwen d0 to d15 ( t rc = 4 ) internal smcclk (not output from external pin)
tmpa901cm tmpa901cm- 833 2010-07-29 (2) asynchronous memory write cycle (t wc = 4, t wp = 2) a0 to a23 d0 to d15 smcben bls = 1 smccsn smcwen t ww t dw t aw t sbw data out p ut t w a t wd smcoen t oeo t sds internal smcclk (not output from external pin) t cl t cyc t ch (t wc = 4 ) smcben bls = 0
tmpa901cm tmpa901cm- 834 2010-07-29 4.3.2 ddr sdram controller ac electrical characteristics ac measurement conditions ? the letter ?t? used in the equations in the tabl e represents the period of internal bus frequency (f hclk ), which is one-half of the cpu clock (f fclk ). ? output level: high = 0.7 dvccm, low = 0.3 dvccm ? input level: high = 0.9 dvccm, low = 0.1 dvccm ? clock output differential level (vod): vod = 0.6 dvccm ? clock output differential crosspoint level (vox): high = 0.6 dvccm, low = 0.4 dvccm note 1: only ddr sdram devices of lvcmos type are s upported. ddr sdram devices of sstil (2.5 v) type are not supported. note 2: the ?equation? column in the table s hows the specifications under the conditions dvccm = 1.7 to 1.9 v and dvcc1a = dvcc1b = dvcc1c = 1.4 to 1.6 v. symbol parameter min typ. max unit condition vix ac differential cross point voltage 0.4 dvccm 0.6 dvccm 1.7 dvccm 1.9v equation no. parameter symbol min max 100 mhz 96 mhz unit 1 dmcdclkp/ dmcdclkn cycle time note) t ck t 10 10.4 2 dmcdclkp&dmcdclkn clock skew time -0.35 0.35 3 clk differential crosspoint cycle t ch 0.5t - 0.5 4.5 4.7 4 clk differential crosspoint cycle t cl 0.5t - 0.5 4.5 4.7 5 dmcddqsx access time from clk(cl* = 3) t ac1 2t-13.5 6.5 7.3 6 data access time from clk(cl* = 3) t ac2 2t-13.5 6.5 7.3 7 dqs to data skew time t dqsq 0 0.7 0.7 0.7 8 address set-up time t as 0.5t - 3.0 2.0 2.2 9 address hold time t ah 0.5t - 3.0 2.0 2.2 10 cke set-up time t cks 0.5t - 3.0 2.0 2.2 11 command set-up time t cms 0.5t - 3.0 2.0 2.2 12 command hold time t cmh 0.5t - 3.0 2.0 2.2 13 data setup time t ds 0.25t - 1.5 1.0 1.1 14 data hold time t dh 0.25t - 1.5 1.0 1.1 15 dmcddm setup time t ms 0.25t - 1.5 1.0 1.1 16 dmcddm hold time t mh 0.25t - 1.5 1.0 1.1 17 write command to 1'st dqs latching transition t dqss 0.75t 1.25t 7.50 to 12.5 7.80 to 13.0 ns * cl = cas latency in case of ddr_sdram, cl number counting method is defferent with sdr_sdram. memory controller cl number = ( ddr_sdram?s cl number ) ? 1 note: the internal bus cycle is t=10ns minimum va lue when the guaranteed temperature is 0 to 70 degree. the internal bus cycle is t=13.3ns minimum value wh en the guaranteed temperature is -20 to 85 degree.
tmpa901cm tmpa901cm- 835 2010-07-29 measuring condition connection 1. dvcc3io 0.7 seldvccm dvcc3io 2. dvcc3io 0.7 selmemc dvcc3io 3. dmcclkin pin connect to dmcdclkp software configuration 1. pmcdrv = 0y11 (full drive) 2. dmc_user_config_5 = 0x0000_0058 loaded capacitance dmcdclkp pin and dmcdclkn pin: cl = 15pf others: cl = 25 pf
tmpa901cm tmpa901cm- 836 2010-07-29 (1) ddr sdram read timing (2-word read mode, memory?s cas latency = 3 memory controller?s cas latency = 2) a 0 to a15 d0 to d15 dmcap t cms t cmh t cms t cmh t ah t as t as t ah t ac2 dmccsx dmcrasn dmccasn dmcwen dmcddmx dmcddqsx t ac1 t ac1 t ac2 t dqsq input input input dmcdclkp t ck dmcdclkn t ch t cl cl=1 cl=2 vod vox act read cmd
tmpa901cm tmpa901cm- 837 2010-07-29 (2) ddr sdram write timing (2-word write mode) a 0 to a15 d0 to d15 dmcap t cms t cmh t cms t cmh t ah t as t as t ah t ds dmccsn dmcrasn dmccasn dmcwen dmcddmx dmcddqsx t dh t cms t cmh t ds t dh t ms t mh t ms t mh t dqss output output output output output dmcdclkp t ch t cl t ck dmcdclkn vod vox write cmd act
tmpa901cm tmpa901cm- 838 2010-07-29 4.3.3 mobile sdr sdram controller ac electrical characteristics ac measurement conditions ? the letter ?t? used in the equations in the tabl e represents the period of internal bus frequency (f hclk ), which is one-half of the cpu clock (f fclk ). ? output level: high = 0.7 dvccm, low = 0.3 dvccm ? input level: high = 0.9 dvccm, low = 0.1 dvccm note: the ?equation? column in the table show s the specifications under the conditions dvccm = 1.7 to 1.9 v and dvcc1a = dvcc1b = dvcc1c = 1.4 to 1.6 v. equation no. parameter symbol min max 100 mhz 96mhz unit 1 clk cycle time t ck t 10 10.4 2 dmcsclk high level width t ch 0.5t - 1.5 3.5 3.7 3 dmcsclk low level width t cl 0.5t - 1.5 3.5 3.7 4 access time from clk(cl * ? = 2) t ac t ? 4.0 6.0 6.4 5 data hold time from internal read t hr 2.0 2.0 2.0 6 data setup time t ds 0.5t ? 3.0 2.0 2.2 7 data hold time t dh 0.5t ? 4.0 ? ? 8 address setup time t as 0.5t ? 3.0 1.0 1.2 9 address hold time t ah 0.5t ? 4.0 ? ? 10 cke setup time t cks 0.5t ? 3.0 2.0 2.2 11 command setup time t cms 0.5t ? 3.0 1.0 1.2 12 command hold time t cmh 0.5t ? 4.0 ? ? ns * cl = cas latency measuring condition connection 1. dvsscomx seldvccm dvcc3io 0.3 2. dvsscomx selmemc dvcc3io 0.3 3. dmcclkin pin connect to dvsscomx software configuration 1. pmcdrv = 0y11 (full drive) 2. dmc_user_config_3 = 0x0000_0000 (16bit bus width memory) loaded capacitance dmcsclk pin: cl = 15pf others: cl = 25 pf note: the internal bus cycle is t=10ns minimum va lue when the guaranteed temperature is 0 to 70 degree. the internal bus cycle is t=13.3ns minimum value wh en the guaranteed temperature is -20 to 85 degree.
tmpa901cm tmpa901cm- 839 2010-07-29 4.3.4 sdr sdram controller electrical characteristics ac measurement conditions ? the letter ?t? used in the equations in the tabl e represents the period of internal bus frequency (f hclk ), which is one-half of the cpu clock (f fclk ). ? output level: high = 0.7 dvccm, low = 0.3 dvccm ? input level: high = 0.9 dvccm, low = 0.1 dvccm note: the ?equation? column in the table show s the specifications under the conditions dvccm = 3.0 to 3.6 v and dvcc1a = dvcc1b = dvcc1c = 1.4 to 1.6 v. equation unit no. parameter symbol min max 100 mhz 96 mhz 1 clk cycle time t ck t 10 10.4 2 dmcsclk high level width t ch 0.5t ? 1.5 3.5 3.7 3 dmcsclk low level width t cl 0.5t ? 1.5 3.5 3.7 4 access time from clk(cl* = 2) t ac t ? 4.0 6.0 6.4 5 data hold time from internal read t hr 2.0 2.0 2.0 6 data set-up time t ds 0.5t ? 3.0 2.0 2.2 7 data hold time t dh 0.5t ? 4.0 1.0 1.2 8 address set-up time t as 0.5t ? 3.0 2.0 2.2 9 address hold time t ah 0.5t ? 4.0 1.0 1.2 10 cke set-up time t cks 0.5t ? 3.0 2.0 2.2 11 command set-up time t cms 0.5t ? 3.0 2.0 2.2 12 command hold time t cmh 0.5t ? 4.0 1.0 1.2 ns * cl = cas latency measuring condition connection 1. dvcc3io 0.7 seldvccm dvcc3io 2. dvsscomx selmemc dvcc3io 0.3 3. dmcclkin pin connect to dvsscomx register 1. pmcdrv = 0y11 (full drive) 2. dmc_user_config3 = 0x0000_0000 (16bit bus width memory) loaded capacitance dmcsclk pin: cl = 15pf others: cl = 25 pf note: the internal bus cycle is t=10ns minimum va lue when the guaranteed temperature is 0 to 70 degree. the internal bus cycle is t=13.3ns minimum value wh en the guaranteed temperature is -20 to 85 degree.
tmpa901cm tmpa901cm- 840 2010-07-29 (1) sdram read timing (cas latency = 2) dmcsclk dmcsdqmx a 0 to a15 d0 to d15 dmcap t ch t cl t ck t cms t cmh t cms t cmh t ah t as t as t ah data input t ac t hr dmcscsn dmcrasn dmccasn dmcwen act read cmd cl = 1 cl = 2
tmpa901cm tmpa901cm- 841 2010-07-29 (2) sdram write timing t ch t cl t ck t cms t cms t cmh data output t ds t dh t cmh t ah t as t as t ah dmcsclk dmcsdqmx a 0 to a15 d0 to d15 dmcap dmcscsn dmcrasn dmccasn dmcwen act write cmd
tmpa901cm tmpa901cm- 842 2010-07-29 (3) sdram burst read timing (burst cycle start, cas latency = 2) t ck t cms t cmh t cmh t ah t as data input t ac t cmh t cms t cms t ah t as t as t ac t ac data input data input t hr t hr dmcsclk dmcsdqmx a 0 to a15 d0 to d15 dmcap dmcscsn dmcrasn dmccasn dmcwen read cmd
tmpa901cm tmpa901cm- 843 2010-07-29 (4) sdram burst read timing (burst timing end) t ck t cms t cmh data input t cmh t cms t cms t ac data input t hr t hr t cmh t as dmcsclk dmcsdqmx a 0 to a15 d0 to d15 dmcap dmcscsn dmcrasn dmccasn dmcwen t ac t ah
tmpa901cm tmpa901cm- 844 2010-07-29 (5) sdram initialization timing t ck t cms t cmh t cms t cmh t cmh t cms t as t ah t cmh t cms dmcsclk dmcsdqmx a 0 to a15 dmcap dmcscsn dmcrasn dmccasn dmcwen
tmpa901cm tmpa901cm- 845 2010-07-29 (6) sdram refresh timing (7) sdram self-refresh timing t ck t rc t cmh t cms t ck t cmh t cms t cks t cks dmcsclk dmcsdqmx dmcscsn dmcrasn dmccasn dmcwen dmcsclk dmcsdqmx dmcscsn dmcrasn dmccasn dmcwen dmccke
tmpa901cm tmpa901cm- 846 2010-07-29 4.3.5 nand flash controller ac electrical characteristics ac measurement conditions ? the letter ?t? used in the equations in the tabl e represents the period of internal bus frequency (f hclk ), which is one-half of the cpu clock (f fclk ). ? output level: high = 0.7 dvcc3io, low = 0.3 dvcc3io ? input level: high = 0.9 dvcc3io, low = 0.1 dvcc3io note 1: the ?equation? column in the table show s the specifications under the conditions dvcc3io = 3.0 to 3.6 v and dvcc1a = dvcc1b = dvcc1c = 1.4 to 1.6 v. note 2: the letter ?n? in the equations represents the value set in ndfmcr2, the letter ?m? the value set in ndfmcr2, the letter ?k? the value in ndfmcr2, and the letter ?l? the value in ndfmcr2. care should be taken not to use values that produce negative results. equation no. symbol parameter min max 100 mhz (n=3) (m=3) (k=3) (l=3) 96 mhz (n=3) (m=3) (k=3) (l=3) unit 1-1 t rc read access cycle (n + m) t 60.0 62.5 1-2 t wc write access cycle (k + l) t 60.0 62.5 2 t rp ndren low level pulse width (n) t -10.0 20.0 21.2 3 t rhp ndren high level pulse width (m) t -10.0 20.0 21.2 4 t rea ndren data access time (n) t ? 14 16.0 17.2 5 t oh read data hold time 0 0 0 6 t wp ndwen low level pulse width (k) t -10.0 20.0 21.2 7 t whp ndwen high level pulse width (l) t -10.0 20.0 21.2 8 t ds write data setup time (k) t -10.0 20.0 21.2 9 t dh write data hold time (l) t -10.0 20.0 21.2 ns ac measurement conditions cl = 40 pf data input (basic clock synchronous to internal f hclk ) ndd0 to ndd7 t rp t re a t oh read c y cle data output ndd0 to ndd7 t wp t dh write c y cle t ds splr2:0 = "4" sphr2:0 = "2" splw2:0 = "3" sphw2:0 = "3" ndren ndwen ndren ndwen t rhp t whp
tmpa901cm tmpa901cm- 847 2010-07-29 4.3.6 lcd controller ac measurement conditions ? the letter ?t? used in the equations in the tabl e represents the period of internal bus frequency (f hclk ), which is one-half of the cpu clock (f fclk ). ? output level: high = 0.7 dvcc3lcd, low = 0.3 dvcc3lcd note: the ?equation? column in the table shows the specifications under the conditions dvcc3lcd = 1.8 to 3.6 v and dvcc1a = dvcc1b = dvcc1c = 1.4 to 1.6 v. equation parameter symbol min max 100 mhz (n=3) 96 mhz (n=3) 48mhz (n=2) unit lclcp clock period (nt) t cw 30 30.0 31.25 41.6 lclcp high level pulse width (including phase reversal) t cwh when n = even (nt / 2) ? 5.0 when n = odd ((n-1)t / 2) ? 5.0 5.0 5.4 15.8 lclcp low level pulse width (including phase reversal) t cwl when n = even (nt / 2) ? 5 when n = odd ((n 1)t / 2) ? 5 15.0 15.8 15.8 data valid to lclcp fall (including phase reversal) t dsu when n = even (nt / 2) ? 6.0 when n = odd ((n-1)t / 2) ? 6.0 4.0 4.4 14.8 lclcp fall to data hold (including phase reversal) t dhd when n = even (nt / 2) ? 6.0 when n = odd ((n 1)t / 2) ? 6.0 14.0 14.8 14.8 ns ac measurement conditions ? cl = 20 pf note: the letter ?n? in the equations represents the value set in lcdtiming2 plus two. the following limitations apply to the ?n? value depending on operating frequency. example 1: when f hclk = 100 mhz, lcdtiming2=0y00000 and =0y00001 (n= 3). example 2: when f hclk = 48 mhz, lcdtiming2=0y00000 and =0y00000 (n= 2). ? lclcp t cwh t cwl t cw ld0 to ld15 t dhd t dsu ld0 to ld15 out t cwh t cwl lcdtiming2 = 0 lcdtiming2 = 1
tmpa901cm tmpa901cm- 848 2010-07-29 4.3.7 ssp controller ac measurement conditions ? the letter ?t? used in the equations in the table represents the period of internal bus frequency (f pclk ), which is one-half of the cpu clock (f fclk ). the internal bus cycle is t=10ns minimum value when the guaranteed temperature is 0 to 70 degree. the internal bus cycle is t=13.3ns minimum value when the guaranteed temperature is -20 to 85 degree. ? output level: high = 0.7 dvc3iom, low = 0.3 dvcc3io ? input level: high = 0.9 dvcc3io, low = 0.1 dvcc3io note: the ?equation? column in the table show s the specifications under the conditions dvcc3io = 3.0 to 3.6 v and dvcc1a = dvcc1b = dvcc1c = 1.4 to 1.6 v. equation parameter symbol min max pclk 100mhz (m=6 n=12) pclk 96mhz (m=6 n=12) unit spxclk period (master) t m (m)t however more than 50ns 60.0 62.5 spxclk period (slave) t s (n)t 120.0 125.0 spxclk rise up time t r 10.0 10.0 10.0 spxclk fall down time t f 10.0 10.0 10.0 master mode: spxclk low level pulse width t wlm (m)t / 2 - 7.0 23.0 24.3 master mode: spxclk high level pulse width t whm (m)t / 2 ?7.0 23.0 24.3 slave mode: spxclk low level pulse width t wls (n)t / 2 - 7.0 53.0 55.5 slave mode: spxclk high level pulse width t whs (n)t / 2 - 7.0 53.0 55.5 master mode: spxclk rise/fall to output data valid t odsm 15.0 15.0 15.0 master mode: spxclk rise/fall to output data hold t odhm (m)t/2 -10 20.0 21.3 master mode: spxclk rise/fall to input data valid delay time t idsm (m)t /2 - 20 10.0 11.2 master mode: spxclk rise/fall to input data hold t idhm 5.0 5.0 5.0 master mode: spxfss valid to spxclk rise/fall t ofsm (m)t -10 (m)t + 10 5070 52.5 72.5 slave mode: spxclk rise/fall to output data valid delay time t odss (3t) + 25 55.0 56.3 slave mode: spxclk rise/fall to output data hold t odhs note1) (n)t /2 + (2t) 80.0 83.3 slave mode: spxclk rise/fall to input data valid delay time t idss (n)t /2 + (3t) - 10.0 80.0 83.8 slave mode: spxclk rise/fall to input data hold t idhs (3t) + 10 40.0 41.3 slave mode: spxfss valid to spxclk rise/fall t ofss (n)t 120 125 ns note1: baud rate clock is set under below condition master mode m = ( (1 + )) = f pclk /spxclk is set only even number and ?m? must set during 65204 m 2 slave mode n = f pclk /spxclk (65204 n 12 ) ac measurement conditions: load capacitance cl = 25 pf ?
tmpa901cm tmpa901cm- 849 2010-07-29 ? ssp spi mode (master) * f pclk 2 spxclk (max) * f pclk 65204 spxclk (min) (1) master sspxcr0 = 0 (data is latched on the first edge.) ? ssp spi mode (master) (2) master sspxcr0 = 1 (data is latched on the second edge.) spxclk output (master) (sspxcr0 = 0) spxdo output t m t r t f t wl t wh t idsm t idhm spxdi input spxclk output (master) (sspxcr0 = 1) spxfss output t ofsm spxclk output (master) (sspxcr0 = 1) t m t r t f t wl t wh t idsm t idhm spxclk output (master) (sspxcr0 = 0) spxfss output t ofsm spxdo output spxdi input t odsm t odhm t odsm t odhm t odsm internal clock state internal clock state
tmpa901cm tmpa901cm- 850 2010-07-29 ? ssp spi mode (slave) * f pclk 12 spxclk (max) * f pclk ? 65204 spxclk (min) (3) slave sspxcr0 = 0 (data is latched on the first edge.) ? ssp spi mode (slave) (4) slave sspxcr0 = 1 (data is latched on the second edge.) spxclk input (sspxcr0 = 0) t s t r t f t wl t wh t idss t idhs spxclk input (sspxcr0 = 1) spxfss input t ofss spxclk input (sspxcr0 = 1) spxclk input (sspxcr0 = 0) spxfss input spxdi input spxdo output t odss t odhs spxdi input spxdo output t s t r t f t wl t wh t idss t idhs t ofss t odss t odhs
tmpa901cm tmpa901cm- 851 2010-07-29 4.3.8 i 2 s ac measurement conditions ? the letter ?t? used in the equations in the table represents the period of internal bus frequency (f pclk ), which is one-half of the cpu clock (f fclk ). f pclk 16 i2sxsclk. ? the letter ?t? used in the equations in th e table represents the period of frequency (f osch ). ? output level: high = 0.7 dvcc3i2s, low = 0.3 dvcc3i2s ? input level: high = 0.9 dvcc3i2s, low = 0.1 dvcc3i2s note: the ?equation? column in the table shows the specifications under the conditions dvcc3i2s = 1.8 to 3.6 v and dvcc1a = dvcc1b = dvcc1c = 1.4 to 1.6 v. in slave mode, the stabilization time is required after i2sxclk input. equation parameter symbol min max 100mhz 96 mhz unit i2smclk out f osch f mc t /4 25 24 24 mhz i2sxmclk high level pulse width t wmh 10 ? 10 10 i2sxmclk low level pulse width t wml 10 ? 10 10 i2sxclk clock output period f sckm 333 ? 333 333 i2sxclk clock input period f scks 160 ? 160 160 i2sxclk high level pulse width t wh 0.45 f sckm ? 149 149 i2sxclk low level pulse width t wl 0.45 f sckm ? 149 149 master mode: i2s1dato, i2sxws hold time t htrm 0.5 f sckm + 2t ? 186 187 master mode: i2s1dato, i2sxws delay time t dtrm ? 0.5 f sckm + 3t + 10 206 207 master mode: i2s0dati setup time t srm 10.0 ? 10 10 master mode: i2s0dati hold time t hrm 0.2 f sckm ? 66 66 master mode: i2sxmclk, i2sxsclk delay time t dly1 ? 10.0 10 10 slave mode: i2s1dato, i2sxws hold time t htrs 0.5 f scks + 2t ? 100 100 slave mode: i2s1dato, i2sxws delay time t dtrs ? 0.8 f scks + 3t + 20 178 179 slave mode: i2s0dati setup time t srs 10.0 ? 10 10 slave mode i2s0dati hold time t hrs 0.2 f scks ? 32 32 ns ac measurement conditions: load capacitance cl = 25 pf
tmpa901cm tmpa901cm- 852 2010-07-29 (1) i 2 s master mode (2) i 2 s slave mode i2s1dato output i2s0dati input i2sxmclk output i2sxws output i2sxsclk output i2s1dato output i2s0dati input i2sxws input i2sxsclk input f mc 0.3v cc 0.7 v cc t wml t wmh t hrm t wl t wh t srm t htrm t dtrm t dly1 t hrs t wl t wh t srs t htrs t dtrs
tmpa901cm tmpa901cm- 853 2010-07-29 4.4 ad conversion characteristics note: ?caltulation? of following table is effective in a range of avcc3ad = 3.0v to 3.6v, dvcc1a = dvcc1b = dvcc1c = 1.4 to 1.6v. parameter symbol condition min typ max unit analog reference voltage ( + ) vrefh avcc3ad avcc3ad avcc3ad analog reference voltage ( ? ) vrefl dvsscomn dvsscomn dvsscomn ad converter power supply voltage avcc3ad 3.0 3.3 3.6 ad converter gnd avss dvsscomn dvsscomn dvsscomn analog input voltage avin vrefl vrefh v irefon =? 1 2.1 3.5 ma analog reference voltage power supply current irefoff = 0 0.1 10 a full scale error efull +1 -1 to +4 lsb offset error eoff \ 3 -4 to +1 lsb differential error ednl -1 to +2 2 lsb integral error einl -2 to +3 3 lsb note 1: error = (?conversion result? ? ?theoretical value?) 1 lsb = (vrefh ? vrefl)/1024[v] note 2: the quantization error does not include. note 3: minimum operating frequency the minimum operating clock and maximum operating cl ock (adclk) of the ad converter is 3 mhz and 33 mhz, respectively. (3mhz ? adclk ? 33mhz) minimum conversion time is 1.39 s at 33mhz, and maximum conversion time is 15.3 s at 3mhz.
tmpa901cm tmpa901cm- 854 2010-07-29 4.5 usb host controller avcc3h = 3.3 0.3 v / f usb = 48 mhz ? ? min max g q hdp, hdm rising time t r 4 20 full speed hdp, hdm falling time t f 4 20 ns full speed differential common mode range vdi 0.2 (hdp) ?(hdm) output signal crossover voltage v crs 1.3 2.0 v v ac measurement conditions full speed tmpa901cmxbg r1 = 27 r1 = 27 r2 = 15 k cl = 50 pf r3 = 1.5 k v cc measuring point hdp, hd v crs 90% 90% 10% 10% t r t f v di hdp hdm
tmpa901cm tmpa901cm- 855 2010-07-29 4.6 recommended oscillation circuit the tmpa901cm is evaluated by using the resonators shown below. please use this information when selecting the resonator to be used. note: the total load capacitance of the oscillation pins is the sum of the exte rnal (or internal) load capacitances c1and c2 and the stray capacitance on the circuit board. even if the recommended c1 and c2 constants are used, the total load capacitance may vary with each board. in board design, the patterns around the oscillation circuit must be as short as possibl e. we also recommend that oscillat ion evaluations be performed on the actual board to be used. (1) connection example (2) recommended ceramic resonator: kyocera kinseki corporation the table below shows the recommended ci rcuit constants for the high-frequency oscillation circuit. note 1: constants c1 and c2 indicates va lues for the built-in load capacitance type. note 2: the part numbers and specifications of kyocera? s products are updated as occasion requires. for details, please check the website of murata. http://global.kyocera.com/ note 3: when the ceramic resonator is used for high-fr equency oscillator circuit, u sb device and host controller requires using the clock in high precision. in this case, the clock of x1usb pin should be used the clock precision is 24mhz 100ppm. (3) recommended crystal low-frequency resonator: kyocera kinseki corporation the table below shows the recommended circuit constants of the low-frequency oscillation circuit. note: the part numbers and specifications of kyocera kinseki?s products are updated as occasion requires. for details, please check the website of kyocera kinseki. http://global.kyocera.com/ recommended constants recommended operating conditions mcu oscillation frequency [mhz] type recommended resonator c1 [pf] c2 [pf] rd [ ] rf [ ] power supply voltage range [v] temperature range [ c] 27.000 smd cx2520sb27000b0hlqz1 6 6 tmpa900cmxbg 24.000 smd cx2520sb24000c0hlqz1 7 7 0 open 1.4 to 1.6 -20 to 85 recommended constants recommended operating conditions mcu oscillation frequency [khz] recommended resonator c1 [pf] c2 [pf] rd [ ] rf [ ] power supply voltage range [v] temperature range [ c] tmpa901cmxbg 32.768 st3215sb 7 7 820 built-in 3.0 to 3.6 -20 to 85 x1 x2 rd rf c2 c1 connection diagram of high-frequency oscillator xt1 xt2 rd c2 c1 connection diagram of low-frequency oscillator rf
tmpa901cr tmpa901cm- 856 2010-07-29 5. package dimensions package name: p-fbga177-1313-0.8c4 unit: mm
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